Datasheet AD8338 (Analog Devices) - 5

link to page 13 link to page 13 link to page 15 link to page 14
Data Sheet AD8338 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS N C EF BAT AG VR V OFS V 16 15 14 13 INPR 1 12 FBKP INPD 2 AD8338 11 OUTP TOP VIEW INMD 3 10 OUTM (Not to Scale) INMR 4 9 FBKM 5 6 7 8 M IN O M DE T O GA CO M DE NOTES
002
1. THE EXPOSED PAD SHOULD BE TIED TO A QUIET ANALOG GROUND.
1279- 1 Figure 3. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
0 EPAD Exposed Pad. The exposed pad should be tied to a quiet analog ground. 1 INPR Positive 500 Ω Resistor Input for Voltage Input Applications. 2 INPD Positive Input for Current Input Applications. 3 INMD Negative Input for Current Input Applications. 4 INMR Negative 500 Ω Resistor Input for Voltage Input Applications. 5 COMM Ground. 6 MODE Gain Mode. This pin selects positive or negative gain slope for gain control. When this pin is tied to VBAT, the gain of the AD8338 increases proportionally with an increase of the voltage on the GAIN pin. When this pin is tied to COMM, the gain decreases with an increase of the voltage on the GAIN pin. 7 GAIN Gain Control Input, 12.5 mV/dB or 80 dB/V. 8 DETO Detector Output Terminal, ±10 µA. If the AGC feature is not used, tie DETO to COMM. 9 FBKM Negative Feedback Node. For more information, see the FBKP, FBKM, OUTP, and OUTM Pins section. 10 OUTM Negative Output. 11 OUTP Positive Output. 12 FBKP Positive Feedback Node. For more information, see the FBKP, FBKM, OUTP, and OUTM Pins section. 13 VAGC Voltage for Automatic Gain Control Circuit. This pin controls the target rms output voltage for the AGC circuit. For more information, see the AGC Circuit, VAGC Pin section. If the AGC feature is not used, tie VAGC to VREF. 14 OFSN Offset Null Terminal. For more information, see the Offset Correction Circuit, OFSN Pin section. If the offset null feature is not used, tie OFSN to ground; otherwise, a capacitor to VREF is used to set the offset null high-pass corner. 15 VBAT Positive Supply Voltage. 16 VREF Internal 1.5 V Voltage Reference. Rev. A | Page 5 of 20 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications AC Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Introduction Overall Structure of the AD8338 VGA Core Normal Operating Conditions INPR, INMR, INPD, and INMD Pins FBKP, FBKM, OUTP, and OUTM Pins Linear-in-dB Gain Control, GAIN Pin Inversion of the Gain Slope, MODE Pin Offset Correction Circuit, OFSN Pin AGC Circuit, VAGC Pin Internal Reference, Pin VREF Explanation of the Gain Function Effects of Using External Resistors Adjusting The Output Common-Mode Voltage Applications Information Simple On-Off Keyed (OOK) Receiver Interfacing the AD8338 to an ADC Outline Dimensions Ordering Guide