Datasheet AD9625 (Analog Devices) - 2
| Manufacturer | Analog Devices |
| Description | 12-Bit, 2.6 GSPS/2.5 GSPS/2.0 GSPS, 1.3 V/2.5 V Analog-to-Digital Converter |
| Pages / Page | 72 / 2 — AD9625. Data Sheet. TABLE OF CONTENTS |
| Revision | C |
| File Format / Size | PDF / 2.1 Mb |
| Document Language | English |
AD9625. Data Sheet. TABLE OF CONTENTS
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AD9625 Data Sheet TABLE OF CONTENTS
Features .. 1 Numerically Controlled Oscillator .. 33 Applications ... 1 High Bandwidth Decimator ... 33 Functional Block Diagram .. 1 Low Bandwidth Decimator ... 36 General Description ... 1 Digital Outputs ... 37 Product Highlights ... 1 Introduction to the JESD204B Interface ... 37 Revision History ... 3 Functional Overview ... 37 Specifications ... 4 JESD204B Link Establishment ... 39 DC Specifications ... 4 Physical Layer Output .. 43 AC Specifications .. 5 Scrambler ... 43 Digital Specifications ... 6 Tail Bits .. 43 Switching Specifications .. 7 DDC Modes (Single and Dual) .. 43 Timing Specifications .. 7 CheckSum ... 44 Absolute Maximum Ratings .. 9 8-Bit/10-Bit Encoder Control ... 44 Thermal Characteristics .. 9 Initial Lane Alignment Sequence (ILAS) .. 44 ESD Caution .. 9 Lane Synchronization .. 45 Pin Configuration and Function Descriptions ... 10 JESD204B Application Layers... 48 Typical Performance Characteristics ... 16 Frame Alignment Character Insertion .. 51 AD9625-2.0 ... 17 Thermal Considerations .. 51 AD9625-2.5 ... 20 Power Supply Considerations ... 51 AD9625-2.6 ... 24 Serial Port Interface (SPI) .. 52 Equivalent Test Circuits ... 27 Configuration Using the SPI ... 52 Theory of Operation .. 28 Hardware Interface ... 52 ADC Architecture .. 28 Memory Map .. 53 Fast Detect ... 28 Reading the Memory Map Register ... 53 Gain Threshold Operation .. 28 Memory Map Registers ... 53 Test Modes ... 29 Applications Information .. 71 Analog Input Considerations .. 30 Design Guidelines .. 71 Differential Input Configurations .. 30 Power and Ground Recommendations ... 71 Using the ADA4961 ... 30 Clock Stability Considerations ... 71 DC Coupling ... 32 SPI Port .. 71 Clock Input Considerations .. 32 Outline Dimensions ... 72 Digital Downconverters (DDC) ... 33 Ordering Guide .. 72 Frequency Synthesizer and Mixer .. 33 Rev. B | Page 2 of 72 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9625-2.0 AD9625-2.5 AD9625-2.6 EQUIVALENT TEST CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE FAST DETECT GAIN THRESHOLD OPERATION Threshold Operation Threshold Format TEST MODES ANALOG INPUT CONSIDERATIONS DIFFERENTIAL INPUT CONFIGURATIONS USING THE ADA4961 DC COUPLING CLOCK INPUT CONSIDERATIONS Clock Jitter Considerations Clock Duty Cycle Considerations DIGITAL DOWNCONVERTERS (DDC) FREQUENCY SYNTHESIZER AND MIXER NUMERICALLY CONTROLLED OSCILLATOR HIGH BANDWIDTH DECIMATOR LOW BANDWIDTH DECIMATOR DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) Data Streaming Link Setup Parameters 8-Bit/10-Bit Encoder Digital Outputs, Timing, and Controls De-Emphasis PHYSICAL LAYER OUTPUT SCRAMBLER TAIL BITS DDC MODES (SINGLE AND DUAL) CHECKSUM 8-BIT/10-BIT ENCODER CONTROL INITIAL LANE ALIGNMENT SEQUENCE (ILAS) LANE SYNCHRONIZATION Multichip Synchronization Using SYSREF± Timestamp Six Lane Output Mode ADC Output Control Bits on JESD204B Samples SYSREF± Setup and Hold IRQ IRQ Guardband Delays (SYSREF± Setup and Hold) Using Rising/Falling Edges of the CLK to Latch SYSREF± Test Modes JESD204B APPLICATION LAYERS fS × 2, fS × 4, fS × 8 Modes FRAME ALIGNMENT CHARACTER INSERTION THERMAL CONSIDERATIONS POWER SUPPLY CONSIDERATIONS SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP REGISTER Open and Reserved Locations Default Values Logic Levels Transfer Register Map MEMORY MAP REGISTERS APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS CLOCK STABILITY CONSIDERATIONS SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE
AD9625 Data Sheet TABLE OF CONTENTS
Features .. 1 Numerically Controlled Oscillator .. 33 Applications ... 1 High Bandwidth Decimator ... 33 Functional Block Diagram .. 1 Low Bandwidth Decimator ... 36 General Description ... 1 Digital Outputs ... 37 Product Highlights ... 1 Introduction to the JESD204B Interface ... 37 Revision History ... 3 Functional Overview ... 37 Specifications ... 4 JESD204B Link Establishment ... 39 DC Specifications ... 4 Physical Layer Output .. 43 AC Specifications .. 5 Scrambler ... 43 Digital Specifications ... 6 Tail Bits .. 43 Switching Specifications .. 7 DDC Modes (Single and Dual) .. 43 Timing Specifications .. 7 CheckSum ... 44 Absolute Maximum Ratings .. 9 8-Bit/10-Bit Encoder Control ... 44 Thermal Characteristics .. 9 Initial Lane Alignment Sequence (ILAS) .. 44 ESD Caution .. 9 Lane Synchronization .. 45 Pin Configuration and Function Descriptions ... 10 JESD204B Application Layers... 48 Typical Performance Characteristics ... 16 Frame Alignment Character Insertion .. 51 AD9625-2.0 ... 17 Thermal Considerations .. 51 AD9625-2.5 ... 20 Power Supply Considerations ... 51 AD9625-2.6 ... 24 Serial Port Interface (SPI) .. 52 Equivalent Test Circuits ... 27 Configuration Using the SPI ... 52 Theory of Operation .. 28 Hardware Interface ... 52 ADC Architecture .. 28 Memory Map .. 53 Fast Detect ... 28 Reading the Memory Map Register ... 53 Gain Threshold Operation .. 28 Memory Map Registers ... 53 Test Modes ... 29 Applications Information .. 71 Analog Input Considerations .. 30 Design Guidelines .. 71 Differential Input Configurations .. 30 Power and Ground Recommendations ... 71 Using the ADA4961 ... 30 Clock Stability Considerations ... 71 DC Coupling ... 32 SPI Port .. 71 Clock Input Considerations .. 32 Outline Dimensions ... 72 Digital Downconverters (DDC) ... 33 Ordering Guide .. 72 Frequency Synthesizer and Mixer .. 33 Rev. B | Page 2 of 72 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9625-2.0 AD9625-2.5 AD9625-2.6 EQUIVALENT TEST CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE FAST DETECT GAIN THRESHOLD OPERATION Threshold Operation Threshold Format TEST MODES ANALOG INPUT CONSIDERATIONS DIFFERENTIAL INPUT CONFIGURATIONS USING THE ADA4961 DC COUPLING CLOCK INPUT CONSIDERATIONS Clock Jitter Considerations Clock Duty Cycle Considerations DIGITAL DOWNCONVERTERS (DDC) FREQUENCY SYNTHESIZER AND MIXER NUMERICALLY CONTROLLED OSCILLATOR HIGH BANDWIDTH DECIMATOR LOW BANDWIDTH DECIMATOR DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) Data Streaming Link Setup Parameters 8-Bit/10-Bit Encoder Digital Outputs, Timing, and Controls De-Emphasis PHYSICAL LAYER OUTPUT SCRAMBLER TAIL BITS DDC MODES (SINGLE AND DUAL) CHECKSUM 8-BIT/10-BIT ENCODER CONTROL INITIAL LANE ALIGNMENT SEQUENCE (ILAS) LANE SYNCHRONIZATION Multichip Synchronization Using SYSREF± Timestamp Six Lane Output Mode ADC Output Control Bits on JESD204B Samples SYSREF± Setup and Hold IRQ IRQ Guardband Delays (SYSREF± Setup and Hold) Using Rising/Falling Edges of the CLK to Latch SYSREF± Test Modes JESD204B APPLICATION LAYERS fS × 2, fS × 4, fS × 8 Modes FRAME ALIGNMENT CHARACTER INSERTION THERMAL CONSIDERATIONS POWER SUPPLY CONSIDERATIONS SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP REGISTER Open and Reserved Locations Default Values Logic Levels Transfer Register Map MEMORY MAP REGISTERS APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS CLOCK STABILITY CONSIDERATIONS SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE
