Datasheet AD7091 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | 1 MSPS, Ultralow Power 12-Bit ADC in 8-Lead LFCSP |
| Pages / Page | 20 / 4 — AD7091. Data Sheet. Parameter. Test Conditions/Comments. Min. Typ. Max. … |
| Revision | B |
| File Format / Size | PDF / 469 Kb |
| Document Language | English |
AD7091. Data Sheet. Parameter. Test Conditions/Comments. Min. Typ. Max. Unit. TIMING SPECIFICATIONS. Table 2. Parameter
Model Line for this Datasheet
Text Version of Document
link to page 9 link to page 4
AD7091 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
VDD = 3 V 0.324 8 µA VDD = 3 V, TA = −40°C to +85°C 0.324 1.8 µA Power Dissipation VIN = 0 V Normal Mode—Static4 VDD = 5.25 V 50 142 µW VDD = 3 V 27 84 µW Normal Mode—Operational VDD = 5.25 V, fSAMPLE = 1 MSPS 2.4 3 mW VDD = 3 V, fSAMPLE = 1 MSPS 1.1 1.4 mW Power-Down Mode VDD = 5.25 V 2 44 µW VDD = 3 V 1 24 µW 1 Dynamic performance is achieved when SCLK operates in burst mode. Operating a free running SCLK during the acquisition phase degrades dynamic performance. 2 See the Terminology section. 3 Sample tested during initial release to ensure compliance. 4 SCLK is operating in burst mode and CS is idling high. With a free running SCLK and CS pulled low, the IDD static current is increased by 60 µA typical at VDD = 5.25 V.
TIMING SPECIFICATIONS
VDD = 2.09 V to 5.25 V, TA = −40°C to +125°C, unless otherwise noted. Signals are specified from 10% to 90% of VDD with a load capacitance of 12 pF on the output pin.1
Table 2. Parameter Limit at TMIN, TMAX Unit Description
fSCLK 50 MHz max Frequency of serial read clock t1 8 ns max Delay from the end of a conversion until SDO exits the three-state condition t2 7 ns max Data access time after SCLK falling edge t3 0.4 tSCLK ns min SCLK high pulse width t4 3 ns min SCLK to data valid hold time t5 0.4 tSCLK ns min SCLK low pulse width t6 15 ns max SCLK falling edge to SDO high impedance t7 10 ns min CONVST pulse width t8 650 ns max Conversion time t9 6 ns min CS low time before the end of a conversion t10 18 ns max Delay from CS falling edge until SDO exits the three-state condition t11 8 ns min CS high time before the end of a conversion t12 8 ns min Delay from the end of a conversion until the CS falling edge t13 100 µs max Power-up time tQUIET 50 ns min Time between the last SCLK edge and the next CONVST pulse 1 Sample tested during initial release to ensure compliance. Rev. B | Page 4 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT MODES OF OPERATION Normal Mode Power-Down Mode POWER CONSUMPTION Power Consumption in Normal Mode Power Consumption Using a Combination of Normal Mode and Power-Down Mode MULTIPLEXER APPLICATIONS SERIAL INTERFACE BUSY INDICATOR ENABLED BUSY INDICATOR DISABLED SOFTWARE RESET INTERFACING WITH AN 8-/16-BIT SPI BUS OUTLINE DIMENSIONS ORDERING GUIDE
AD7091 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
VDD = 3 V 0.324 8 µA VDD = 3 V, TA = −40°C to +85°C 0.324 1.8 µA Power Dissipation VIN = 0 V Normal Mode—Static4 VDD = 5.25 V 50 142 µW VDD = 3 V 27 84 µW Normal Mode—Operational VDD = 5.25 V, fSAMPLE = 1 MSPS 2.4 3 mW VDD = 3 V, fSAMPLE = 1 MSPS 1.1 1.4 mW Power-Down Mode VDD = 5.25 V 2 44 µW VDD = 3 V 1 24 µW 1 Dynamic performance is achieved when SCLK operates in burst mode. Operating a free running SCLK during the acquisition phase degrades dynamic performance. 2 See the Terminology section. 3 Sample tested during initial release to ensure compliance. 4 SCLK is operating in burst mode and CS is idling high. With a free running SCLK and CS pulled low, the IDD static current is increased by 60 µA typical at VDD = 5.25 V.
TIMING SPECIFICATIONS
VDD = 2.09 V to 5.25 V, TA = −40°C to +125°C, unless otherwise noted. Signals are specified from 10% to 90% of VDD with a load capacitance of 12 pF on the output pin.1
Table 2. Parameter Limit at TMIN, TMAX Unit Description
fSCLK 50 MHz max Frequency of serial read clock t1 8 ns max Delay from the end of a conversion until SDO exits the three-state condition t2 7 ns max Data access time after SCLK falling edge t3 0.4 tSCLK ns min SCLK high pulse width t4 3 ns min SCLK to data valid hold time t5 0.4 tSCLK ns min SCLK low pulse width t6 15 ns max SCLK falling edge to SDO high impedance t7 10 ns min CONVST pulse width t8 650 ns max Conversion time t9 6 ns min CS low time before the end of a conversion t10 18 ns max Delay from CS falling edge until SDO exits the three-state condition t11 8 ns min CS high time before the end of a conversion t12 8 ns min Delay from the end of a conversion until the CS falling edge t13 100 µs max Power-up time tQUIET 50 ns min Time between the last SCLK edge and the next CONVST pulse 1 Sample tested during initial release to ensure compliance. Rev. B | Page 4 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT MODES OF OPERATION Normal Mode Power-Down Mode POWER CONSUMPTION Power Consumption in Normal Mode Power Consumption Using a Combination of Normal Mode and Power-Down Mode MULTIPLEXER APPLICATIONS SERIAL INTERFACE BUSY INDICATOR ENABLED BUSY INDICATOR DISABLED SOFTWARE RESET INTERFACING WITH AN 8-/16-BIT SPI BUS OUTLINE DIMENSIONS ORDERING GUIDE
