Datasheet AD7091 (Analog Devices) - 9

ManufacturerAnalog Devices
Description1 MSPS, Ultralow Power 12-Bit ADC in 8-Lead LFCSP
Pages / Page20 / 9 — Data Sheet. AD7091. TERMINOLOGY Integral Nonlinearity (INL). …
RevisionB
File Format / SizePDF / 469 Kb
Document LanguageEnglish

Data Sheet. AD7091. TERMINOLOGY Integral Nonlinearity (INL). Signal-to-Noise-and-Distortion Ratio (SINAD)

Data Sheet AD7091 TERMINOLOGY Integral Nonlinearity (INL) Signal-to-Noise-and-Distortion Ratio (SINAD)

Model Line for this Datasheet

Text Version of Document

Data Sheet AD7091 TERMINOLOGY Integral Nonlinearity (INL) Signal-to-Noise-and-Distortion Ratio (SINAD)
INL is the maximum deviation from a straight line passing SINAD is the measured ratio of signal to noise and distortion through the endpoints of the ADC transfer function. For the at the output of the ADC. The signal is the rms value of the sine AD7091, the endpoints of the transfer function are zero scale wave, and noise is the rms sum of al nonfundamental signals up (a point 0.5 LSB below the first code transition) and full scale to half the sampling frequency (fSAMPLE/2), including harmonics, (a point 0.5 LSB above the last code transition). but excluding dc.
Differential Nonlinearity (DNL) Total Unadjusted Error (TUE)
DNL is the difference between the measured and the ideal TUE is a comprehensive specification that includes the gain, 1 LSB change between any two adjacent codes in the ADC. linearity, and offset errors.
Offset Error Total Harmonic Distortion (THD)
Offset error is the deviation of the first code transition (00 … 000 THD is the ratio of the rms sum of harmonics to the funda- to 00 … 001) from the ideal (such as GND + 0.5 LSB). mental. For the AD7091, THD is defined as
Gain Error
2 2 2 2 2 + + + + THD (dB) 2 V 3 V 4 V 5 V 6 V Gain error is the deviation of the last code transition (111 … 110 = 20 log 1 V to 111 … 111) from the ideal (such as VDD − 1.5 LSB) after the offset error has been adjusted out. where: V1 is the rms amplitude of the fundamental.
Track-and-Hold Acquisition Time
V2, V3, V4, V5, and V6 are the rms amplitudes of the second The track-and-hold amplifier returns to track mode after the through the sixth harmonics. end of a conversion. The track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to
Spurious-Free Dynamic Range (SFDR)
reach its final value, within ±0.5 LSB, after a conversion. SFDR, also known as peak harmonic or spurious noise, is defined as the ratio of the rms value of the next largest component in the
Signal-to-Noise Ratio (SNR)
ADC output spectrum (up to fSAMPLE/2 and excluding dc) to the SNR is the measured ratio of signal to noise at the output of the rms value of the fundamental. ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling
Aperture Delay
frequency (f Aperture delay is the measured interval between the leading edge of SAMPLE/2), excluding dc. the sampling clock and the point at which the ADC samples data. The ratio is dependent on the number of quantization levels in the digitization process: the more levels, the smal er the quantization
Aperture Jitter
noise. The theoretical signal-to-noise ratio for an ideal N-bit Aperture jitter is the sample-to-sample variation in the effective converter with a sine wave input is given by point in time at which the data is sampled. Signal-to-Noise Ratio = (6.02N + 1.76) dB
Full Power Bandwidth
Ful power bandwidth is the input frequency at which the ampli- Therefore, for a 12-bit converter, the SNR is 74 dB. tude of the reconstructed fundamental is reduced by 0.1 dB or 3 dB for a ful -scale input. Rev. B | Page 9 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT MODES OF OPERATION Normal Mode Power-Down Mode POWER CONSUMPTION Power Consumption in Normal Mode Power Consumption Using a Combination of Normal Mode and Power-Down Mode MULTIPLEXER APPLICATIONS SERIAL INTERFACE BUSY INDICATOR ENABLED BUSY INDICATOR DISABLED SOFTWARE RESET INTERFACING WITH AN 8-/16-BIT SPI BUS OUTLINE DIMENSIONS ORDERING GUIDE