Datasheet Texas Instruments 74AC11074

Manufacturer	Texas Instruments
Series	74AC11074

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Parametrics

Parameters / Models	74AC11074D	74AC11074DE4	74AC11074DR	74AC11074DRG4	74AC11074N	74AC11074PWLE	74AC11074PWR
3-State Output	No	No	No	No	No	No	No
Approx. Price (US$)						0.71 | 1ku
Bits	2	2	2	2	2		2
Bits(#)						2
F @ Nom Voltage(Max), Mhz	100	100	100	100	100		100
F @ Nom Voltage(Max)(Mhz)						100
ICC @ Nom Voltage(Max), mA	0.04	0.04	0.04	0.04	0.04		0.04
ICC @ Nom Voltage(Max)(mA)						0.04
Input Type						CMOS
Operating Temperature Range, C	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85		-40 to 85
Operating Temperature Range(C)						-40 to 85
Output Drive (IOL/IOH)(Max), mA	24/-24	24/-24	24/-24	24/-24	24/-24		24/-24
Output Drive (IOL/IOH)(Max)(mA)						24/-24
Output Type						CMOS
Package Group	SOIC	SOIC	SOIC	SOIC	PDIP	TSSOP	TSSOP
Package Size: mm2:W x L, PKG	14SOIC: 52 mm2: 6 x 8.65(SOIC)	14SOIC: 52 mm2: 6 x 8.65(SOIC)	14SOIC: 52 mm2: 6 x 8.65(SOIC)	14SOIC: 52 mm2: 6 x 8.65(SOIC)	See datasheet (PDIP)		14TSSOP: 32 mm2: 6.4 x 5(TSSOP)
Package Size: mm2:W x L (PKG)						See datasheet (PDIP)
Rating	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog
Schmitt Trigger	No	No	No	No	No	No	No
Technology Family	AC	AC	AC	AC	AC	AC	AC
VCC(Max), V	5.5	5.5	5.5	5.5	5.5		5.5
VCC(Max)(V)						5.5
VCC(Min), V	3	3	3	3	3		3
VCC(Min)(V)						3
Voltage(Nom), V	3.3,5	3.3,5	3.3,5	3.3,5	3.3,5		3.3,5
Voltage(Nom)(V)						3.3 5
tpd @ Nom Voltage(Max), ns	11.4,8.2	11.4,8.2	11.4,8.2	11.4,8.2	11.4,8.2		11.4,8.2
tpd @ Nom Voltage(Max)(ns)						11.4 8.2

Eco Plan

Application Notes

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  PDF, 150 Kb, File published: Oct 1, 1996
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  PDF, 337 Kb, File published: Jul 8, 2004
  Forty-eight-pin TSSOP components that were packaged using Texas Instruments (TI) standard packing methodology were subjected to electrical discharges between 0.5 and 20 kV as generated by an IEC ESD simulator to determine the level of ISD protection provided by the packing materials. The testing included trays tape and reel and magazines. Additional units were subjected to the same discharge
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  PDF, 614 Kb, Revision: C, File published: Dec 2, 2015
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  PDF, 380 Kb, File published: Aug 29, 2002
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  PDF, 89 Kb, Revision: B, File published: Jun 1, 1997
  Reduction of power consumption makes a device more reliable. The need for devices that consume a minimum amount of power was a major driving force behind the development of CMOS technologies. As a result CMOS devices are best known for low power consumption. However for minimizing the power requirements of a board or a system simply knowing that CMOS devices may use less power than equivale
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  PDF, 1.7 Mb, File published: Oct 1, 1996
  This report contains a comprehensive collection of the input and output characteristic curves of typical integrated circuits from various logic families. These curves go beyond the information given in data sheets by providing additional details regarding the characteristics of the components. This knowledge is particularly useful when for example a decision must be made as to which circuit shou
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  PDF, 34 Kb, Revision: A, File published: Feb 6, 2015
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  PDF, 186 Kb, Revision: C, File published: Jun 1, 1997
  Data sheets which usually give information on device behavior only under recommended operating conditions may only partially answer engineering questions that arise during the development of systems using logic devices. However information is frequently needed regarding the behavior of the device outside the conditions in the data sheet. Such questions might be:?How does a bus driver behave w
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  Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
  PDF, 43 Kb, File published: Apr 1, 1996
  Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren
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  Shelf-Life Evaluation of Lead-Free Component Finishes
  PDF, 1.3 Mb, File published: May 24, 2004
  The integrated circuit (IC) industry is converting to lead (Pb)-free termination finishes for leadframe-based packages. IC component users need to know the maximum length of time that components can be stored prior to being soldered. This study predicts shelf life of the primary Pb-free finishes being proposed by the industry. Components were exposed to a controlled environment, with known aging a

Model Line

Manufacturer's Classification

• Semiconductors> Logic> Flip-Flop/Latch/Register> D-Type Flip-Flop