Datasheet Texas Instruments CD74HCT73
| Manufacturer | Texas Instruments |
| Series | CD74HCT73 |
High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset
Datasheets
CD54HC73, CD74HC73, CD74HCT73 datasheet
PDF, 724 Kb, Revision: E, File published: Aug 21, 2003
Extract from the document
Prices
Status
| CD74HCT73E | CD74HCT73EE4 | CD74HCT73M | CD74HCT73MG4 | |
|---|---|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No | No | No | No |
Packaging
| CD74HCT73E | CD74HCT73EE4 | CD74HCT73M | CD74HCT73MG4 | |
|---|---|---|---|---|
| N | 1 | 2 | 3 | 4 |
| Pin | 14 | 14 | 14 | 14 |
| Package Type | N | N | D | D |
| Industry STD Term | PDIP | PDIP | SOIC | SOIC |
| JEDEC Code | R-PDIP-T | R-PDIP-T | R-PDSO-G | R-PDSO-G |
| Package QTY | 25 | 25 | 50 | 50 |
| Carrier | TUBE | TUBE | TUBE | TUBE |
| Device Marking | CD74HCT73E | CD74HCT73E | HCT73M | HCT73M |
| Width (mm) | 6.35 | 6.35 | 3.91 | 3.91 |
| Length (mm) | 19.3 | 19.3 | 8.65 | 8.65 |
| Thickness (mm) | 3.9 | 3.9 | 1.58 | 1.58 |
| Pitch (mm) | 2.54 | 2.54 | 1.27 | 1.27 |
| Max Height (mm) | 5.08 | 5.08 | 1.75 | 1.75 |
| Mechanical Data | Download | Download | Download | Download |
Parametrics
| Parameters / Models | CD74HCT73E | CD74HCT73EE4 | CD74HCT73M | CD74HCT73MG4 |
|---|---|---|---|---|
| Bits | 2 | 2 | 2 | 2 |
| F @ Nom Voltage(Max), Mhz | 25 | 25 | 25 | 25 |
| ICC @ Nom Voltage(Max), mA | 0.04 | 0.04 | 0.04 | 0.04 |
| Output Drive (IOL/IOH)(Max), mA | -6/6 | -6/6 | -6/6 | -6/6 |
| Package Group | PDIP | PDIP | SOIC | SOIC |
| Package Size: mm2:W x L, PKG | See datasheet (PDIP) | See datasheet (PDIP) | 14SOIC: 52 mm2: 6 x 8.65(SOIC) | 14SOIC: 52 mm2: 6 x 8.65(SOIC) |
| Rating | Catalog | Catalog | Catalog | Catalog |
| Schmitt Trigger | No | No | No | No |
| Technology Family | HCT | HCT | HCT | HCT |
| VCC(Max), V | 5.5 | 5.5 | 5.5 | 5.5 |
| VCC(Min), V | 4.5 | 4.5 | 4.5 | 4.5 |
| Voltage(Nom), V | 5 | 5 | 5 | 5 |
| tpd @ Nom Voltage(Max), ns | 48 | 48 | 48 | 48 |
Eco Plan
| CD74HCT73E | CD74HCT73EE4 | CD74HCT73M | CD74HCT73MG4 | |
|---|---|---|---|---|
| RoHS | Compliant | Compliant | Compliant | Compliant |
| Pb Free | Yes | Yes |
Application Notes
- Power-Up Behavior of Clocked Devices (Rev. A)PDF, 34 Kb, Revision: A, File published: Feb 6, 2015
Model Line
Series: CD74HCT73 (4)
Manufacturer's Classification
- Semiconductors> Logic> Flip-Flop/Latch/Register> J-K Flip-Flop
