Datasheet Texas Instruments CDCE72010
| Manufacturer | Texas Instruments |
| Series | CDCE72010 |
10 Outputs Low Jitter Clock Synchronizer and Jitter Cleaner
Datasheets
Ten Output High Performance Clock Synchronizer, Jitter Cleaner &Clock Distrib datasheet
PDF, 1.8 Mb, Revision: C, File published: Jan 31, 2012
Extract from the document
Prices
Status
| CDCE72010RGCR | CDCE72010RGCRG4 | CDCE72010RGCT | CDCE72010RGCTG4 | |
|---|---|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes | Yes | No | No |
Packaging
| CDCE72010RGCR | CDCE72010RGCRG4 | CDCE72010RGCT | CDCE72010RGCTG4 | |
|---|---|---|---|---|
| N | 1 | 2 | 3 | 4 |
| Pin | 64 | 64 | 64 | 64 |
| Package Type | RGC | RGC | RGC | RGC |
| Industry STD Term | VQFN | VQFN | VQFN | VQFN |
| JEDEC Code | S-PQFP-N | S-PQFP-N | S-PQFP-N | S-PQFP-N |
| Package QTY | 2000 | 2000 | 250 | 250 |
| Carrier | LARGE T&R | LARGE T&R | SMALL T&R | SMALL T&R |
| Device Marking | CDCE72010 | CDCE72010 | CDCE72010 | CDCE72010 |
| Width (mm) | 9 | 9 | 9 | 9 |
| Length (mm) | 9 | 9 | 9 | 9 |
| Thickness (mm) | .88 | .88 | .88 | .88 |
| Pitch (mm) | .5 | .5 | .5 | .5 |
| Max Height (mm) | 1 | 1 | 1 | 1 |
| Mechanical Data | Download | Download | Download | Download |
Parametrics
| Parameters / Models | CDCE72010RGCR | CDCE72010RGCRG4 | CDCE72010RGCT | CDCE72010RGCTG4 |
|---|---|---|---|---|
| Divider Ratio | 1 to 80 | 1 to 80 | 1 to 80 | 1 to 80 |
| Input Level | LVCMOS,LVDS,LVPECL | LVCMOS,LVDS,LVPECL | LVCMOS,LVDS,LVPECL | LVCMOS,LVDS,LVPECL |
| Number of Inputs | 2 | 2 | 2 | 2 |
| Number of Outputs | 10 | 10 | 10 | 10 |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 |
| Output Frequency(Max), MHz | 1500 | 1500 | 1500 | 1500 |
| Output Frequency(Min), MHz | 0.001 | 0.001 | 0.001 | 0.001 |
| Output Level | LVCMOS,LVDS,LVPECL | LVCMOS,LVDS,LVPECL | LVCMOS,LVDS,LVPECL | LVCMOS,LVDS,LVPECL |
| Package Group | VQFN | VQFN | VQFN | VQFN |
| Package Size: mm2:W x L, PKG | 64VQFN: 81 mm2: 9 x 9(VQFN) | 64VQFN: 81 mm2: 9 x 9(VQFN) | 64VQFN: 81 mm2: 9 x 9(VQFN) | 64VQFN: 81 mm2: 9 x 9(VQFN) |
| Rating | Catalog | Catalog | Catalog | Catalog |
| Special Features | Integrated EEPROM,Programmable Phase Offset | Integrated EEPROM,Programmable Phase Offset | Integrated EEPROM,Programmable Phase Offset | Integrated EEPROM,Programmable Phase Offset |
| Supply Voltage(Max), V | 3.6 | 3.6 | 3.6 | 3.6 |
| Supply Voltage(Min), V | 3 | 3 | 3 | 3 |
Eco Plan
| CDCE72010RGCR | CDCE72010RGCRG4 | CDCE72010RGCT | CDCE72010RGCTG4 | |
|---|---|---|---|---|
| RoHS | Compliant | Compliant | Compliant | Compliant |
Application Notes
- Using the CDCE72010 as a Frequency SynthesizerPDF, 1.1 Mb, File published: May 31, 2008
This application report is a general guide for using the CDCE72010 as a frequency synthesizer. This document explains the methods to work with the phase-locked loop (PLL) of the CDCE72010 to achieve multiple outputfrequencies from any input frequency. It also describes the basic functionality and methods for using the device efficiently. Furthermore, it describes the clock terminationmethod, d - Clock jitter analyzed in the time domain, Part 2PDF, 588 Kb, File published: Nov 15, 2010
- Impact of sampling-clock spurs on ADC performancePDF, 1.2 Mb, File published: Jul 14, 2009
- Clock jitter analyzed in the time domain, Part 3PDF, 627 Kb, File published: Sep 16, 2011
- 4Q 2010 Issue Analog Applications JournalPDF, 1.3 Mb, File published: Nov 15, 2010
- Q3 2009 Issue Analog Applications JournalPDF, 2.1 Mb, File published: Jul 14, 2009
- 3Q 2011 Issue Analog Applications JournalPDF, 1.4 Mb, File published: Sep 16, 2011
- Журнал по применению аналоговых компонентов 3Q 2011PDF, 3.9 Mb, File published: Sep 1, 2011
- Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Mb, File published: Jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Kb, File published: Jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
Model Line
Series: CDCE72010 (4)
Manufacturer's Classification
- Semiconductors> Clock and Timing> Clock Jitter Cleaners> Single-Loop PLL
