Datasheet Texas Instruments SN74AUP2G00
| Manufacturer | Texas Instruments |
| Series | SN74AUP2G00 |
Low-Power Dual 2-Input Positive-NAND Gate
Datasheets
SN74AUP2G00 Low-Power Dual 2-Input Positive-NAND Gate datasheet
PDF, 1.2 Mb, Revision: C, File published: May 7, 2010
Extract from the document
Prices
Status
| SN74AUP2G00DCUR | SN74AUP2G00DQER | SN74AUP2G00RSER | SN74AUP2G00YFPR | |
|---|---|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes | Yes | Yes | Yes |
Packaging
| SN74AUP2G00DCUR | SN74AUP2G00DQER | SN74AUP2G00RSER | SN74AUP2G00YFPR | |
|---|---|---|---|---|
| N | 1 | 2 | 3 | 4 |
| Pin | 8 | 8 | 8 | 8 |
| Package Type | DCU | DQE | RSE | YFP |
| Industry STD Term | VSSOP | X2SON | UQFN | DSBGA |
| JEDEC Code | R-PDSO-G | R-PSSO-N | S-PQFP-N | R-XBGA-N |
| Package QTY | 3000 | 5000 | 5000 | 3000 |
| Carrier | LARGE T&R | LARGE T&R | LARGE T&R | LARGE T&R |
| Device Marking | H00R | PN | PN | HAN |
| Width (mm) | 2 | 1 | 1.5 | |
| Length (mm) | 2.3 | 1.4 | 1.5 | |
| Thickness (mm) | .85 | .37 | .55 | |
| Pitch (mm) | .5 | .35 | .5 | .4 |
| Max Height (mm) | .9 | .4 | .6 | .5 |
| Mechanical Data | Download | Download | Download | Download |
Parametrics
| Parameters / Models | SN74AUP2G00DCUR | SN74AUP2G00DQER | SN74AUP2G00RSER | SN74AUP2G00YFPR |
|---|---|---|---|---|
| 3-State Output | No | No | No | No |
| Bits | 2 | 2 | 2 | 2 |
| F @ Nom Voltage(Max), Mhz | 100 | 100 | 100 | 100 |
| Gate Type | NAND | NAND | NAND | NAND |
| ICC @ Nom Voltage(Max), mA | 0.0009 | 0.0009 | 0.0009 | 0.0009 |
| Logic | True | True | True | True |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 |
| Output Drive (IOL/IOH)(Max), mA | 4/-4 | 4/-4 | 4/-4 | 4/-4 |
| Package Group | VSSOP | X2SON | UQFN | DSBGA |
| Package Size: mm2:W x L, PKG | 8VSSOP: 6 mm2: 3.1 x 2(VSSOP) | 8X2SON: 1 mm2: 1 x 1.4(X2SON) | 8UQFN: 2 mm2: 1.5 x 1.5(UQFN) | See datasheet (DSBGA) |
| Rating | Catalog | Catalog | Catalog | Catalog |
| Schmitt Trigger | No | No | No | No |
| Special Features | IOFF,low power consumption,low tpd | IOFF,low power consumption,low tpd | IOFF,low power consumption,low tpd | IOFF,low power consumption,low tpd |
| Sub-Family | NAND Gate | NAND Gate | NAND Gate | NAND Gate |
| Technology Family | AUP | AUP | AUP | AUP |
| VCC(Max), V | 3.6 | 3.6 | 3.6 | 3.6 |
| VCC(Min), V | 0.8 | 0.8 | 0.8 | 0.8 |
| Voltage(Nom), V | 0.8,1.2,1.5,1.8,2.5,3.3 | 0.8,1.2,1.5,1.8,2.5,3.3 | 0.8,1.2,1.5,1.8,2.5,3.3 | 0.8,1.2,1.5,1.8,2.5,3.3 |
| tpd @ Nom Voltage(Max), ns | 31.8,26.3,16.6,12.9,8.8,6.7 | 31.8,26.3,16.6,12.9,8.8,6.7 | 31.8,26.3,16.6,12.9,8.8,6.7 | 31.8,26.3,16.6,12.9,8.8,6.7 |
Eco Plan
| SN74AUP2G00DCUR | SN74AUP2G00DQER | SN74AUP2G00RSER | SN74AUP2G00YFPR | |
|---|---|---|---|---|
| RoHS | Compliant | Compliant | Compliant | Compliant |
Application Notes
- Understanding Schmitt TriggersPDF, 80 Kb, File published: Sep 21, 2011
Model Line
Series: SN74AUP2G00 (4)
Manufacturer's Classification
- Semiconductors> Logic> Little Logic
