Datasheet DS18B20 - 10
| Description | Programmable Resolution1-Wire Digital Thermometer |
| Pages / Page | 20 / 10 — 1-Wire Bus System. Transaction Sequence. Hardware Configuration. … |
| File Format / Size | PDF / 496 Kb |
| Document Language | English |
1-Wire Bus System. Transaction Sequence. Hardware Configuration. Initialization. ROM Commands. DS18B20. 1-Wire PORT. Search Rom [F0h]
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link to page 10 link to page 15 link to page 13 DS18B20 Programmable Resolution 1-Wire Digital Thermometer
1-Wire Bus System Transaction Sequence
The 1-Wire bus system uses a single bus master to con- The transaction sequence for accessing the DS18B20 is trol one or more slave devices. The DS18B20 is always a as follows: slave. When there is only one slave on the bus, the sys- Step 1. Initialization tem is referred to as a “single-drop” system; the system is “multidrop” if there are multiple slaves on the bus. Step 2. ROM Command (followed by any required data exchange) All data and commands are transmitted least significant bit first over the 1-Wire bus. Step 3. DS18B20 Function Command (followed by any required data exchange) The following discussion of the 1-Wire bus system is broken down into three topics: hardware configuration, It is very important to follow this sequence every time the transaction sequence, and 1-Wire signaling (signal types DS18B20 is accessed, as the DS18B20 will not respond and timing). if any steps in the sequence are missing or out of order. Exceptions to this rule are the Search ROM [F0h] and
Hardware Configuration
Alarm Search [ECh] commands. After issuing either of The 1-Wire bus has by definition only a single data line. these ROM commands, the master must return to Step 1 Each device (master or slave) interfaces to the data line in the sequence. via an open-drain or 3-state port. This allows each device
Initialization
to “release” the data line when the device is not transmit- ting data so the bus is available for use by another device. All transactions on the 1-Wire bus begin with an initializa- The 1-Wire port of the DS18B20 (the DQ pin) is open tion sequence. The initialization sequence consists of a drain with an internal circuit equivalent to that shown in reset pulse transmitted by the bus master followed by Figure 12. presence pulse(s) transmitted by the slave(s). The pres- ence pulse lets the bus master know that slave devices The 1-Wire bus requires an external pullup resistor of (such as the DS18B20) are on the bus and are ready approximately 5kΩ; thus, the idle state for the 1-Wire to operate. Timing for the reset and presence pulses is bus is high. If for any reason a transaction needs to be detailed in the 1-Wire Signaling section. suspended, the bus MUST be left in the idle state if the transaction is to resume. Infinite recovery time can occur
ROM Commands
between bits so long as the 1-Wire bus is in the inactive After the bus master has detected a presence pulse, it (high) state during the recovery period. If the bus is held can issue a ROM command. These commands operate low for more than 480µs, all components on the bus will on the unique 64-bit ROM codes of each slave device be reset. and allow the master to single out a specific device if many are present on the 1-Wire bus. These commands also allow the master to determine how many and what types of devices are present on the bus or if any device VPU has experienced an alarm condition. There are five ROM commands, and each command is 8 bits long. The master
DS18B20
4.7kΩ device must issue an appropriate ROM command before
1-Wire PORT
Rx 1-Wire BUS DQ issuing a DS18B20 function command. A flowchart for Rx operation of the ROM commands is shown in Figure 13. 5µA Tx TYP
Search Rom [F0h]
100Ω MOSFET When a system is initially powered up, the master must Tx identify the ROM codes of all slave devices on the bus, Rx = RECEIVE which allows the master to determine the number of Tx = TRANSMIT slaves and their device types. The master learns the ROM codes through a process of elimination that requires the master to perform a Search ROM cycle (i.e., Search Figure 12. Hardware Configuration ROM command followed by data exchange) as many times as necessary to identify all of the slave devices. www.maximintegrated.com Maxim Integrated │
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1-Wire Bus System Transaction Sequence
The 1-Wire bus system uses a single bus master to con- The transaction sequence for accessing the DS18B20 is trol one or more slave devices. The DS18B20 is always a as follows: slave. When there is only one slave on the bus, the sys- Step 1. Initialization tem is referred to as a “single-drop” system; the system is “multidrop” if there are multiple slaves on the bus. Step 2. ROM Command (followed by any required data exchange) All data and commands are transmitted least significant bit first over the 1-Wire bus. Step 3. DS18B20 Function Command (followed by any required data exchange) The following discussion of the 1-Wire bus system is broken down into three topics: hardware configuration, It is very important to follow this sequence every time the transaction sequence, and 1-Wire signaling (signal types DS18B20 is accessed, as the DS18B20 will not respond and timing). if any steps in the sequence are missing or out of order. Exceptions to this rule are the Search ROM [F0h] and
Hardware Configuration
Alarm Search [ECh] commands. After issuing either of The 1-Wire bus has by definition only a single data line. these ROM commands, the master must return to Step 1 Each device (master or slave) interfaces to the data line in the sequence. via an open-drain or 3-state port. This allows each device
Initialization
to “release” the data line when the device is not transmit- ting data so the bus is available for use by another device. All transactions on the 1-Wire bus begin with an initializa- The 1-Wire port of the DS18B20 (the DQ pin) is open tion sequence. The initialization sequence consists of a drain with an internal circuit equivalent to that shown in reset pulse transmitted by the bus master followed by Figure 12. presence pulse(s) transmitted by the slave(s). The pres- ence pulse lets the bus master know that slave devices The 1-Wire bus requires an external pullup resistor of (such as the DS18B20) are on the bus and are ready approximately 5kΩ; thus, the idle state for the 1-Wire to operate. Timing for the reset and presence pulses is bus is high. If for any reason a transaction needs to be detailed in the 1-Wire Signaling section. suspended, the bus MUST be left in the idle state if the transaction is to resume. Infinite recovery time can occur
ROM Commands
between bits so long as the 1-Wire bus is in the inactive After the bus master has detected a presence pulse, it (high) state during the recovery period. If the bus is held can issue a ROM command. These commands operate low for more than 480µs, all components on the bus will on the unique 64-bit ROM codes of each slave device be reset. and allow the master to single out a specific device if many are present on the 1-Wire bus. These commands also allow the master to determine how many and what types of devices are present on the bus or if any device VPU has experienced an alarm condition. There are five ROM commands, and each command is 8 bits long. The master
DS18B20
4.7kΩ device must issue an appropriate ROM command before
1-Wire PORT
Rx 1-Wire BUS DQ issuing a DS18B20 function command. A flowchart for Rx operation of the ROM commands is shown in Figure 13. 5µA Tx TYP
Search Rom [F0h]
100Ω MOSFET When a system is initially powered up, the master must Tx identify the ROM codes of all slave devices on the bus, Rx = RECEIVE which allows the master to determine the number of Tx = TRANSMIT slaves and their device types. The master learns the ROM codes through a process of elimination that requires the master to perform a Search ROM cycle (i.e., Search Figure 12. Hardware Configuration ROM command followed by data exchange) as many times as necessary to identify all of the slave devices. www.maximintegrated.com Maxim Integrated │
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