Datasheet MCP6286 (Microchip) - 5

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MCP6286 1.2 Test Circuits
The circuit used for most DC and AC tests is shown in Figure 1-1. It independently sets VCM and VOUT; see CF Equation 1-1. The circuit’s common mode voltage is 6.8 pF (VP + VM)/2, not VCM. VOST includes VOS plus the effects of temperature, CMRR, PSRR and AOL. RG RF
EQUATION 1-1:
100 kΩ 100 kΩ VREF = VDD/2 VP G = R ⁄ R V DM F G DD V G = 1 + G IN+ N DM V = V (1 – 1 ⁄ G ) + V (1 ⁄ G ) C C B1 B2 CM P N REF N
MCP6286
100 nF 1 µF V = V – V OST IN– IN+ V = V + (V – V )G + V G OUT REF P M DM OST N VIN– Where: V V M OUT GDM = Differential Mode Gain (V/V) R R C G RF L L G 10 kΩ 60 pF N = Noise Gain (V/V) 100 kΩ 100 kΩ VCM = Op Amp’s Common Mode (V) Input Voltage CF V V L 6.8 pF OST = Op Amp’s Total Input Offset (mV) Voltage
FIGURE 1-1:
AC and DC Test Circuit for Most Specifications. © 2009 Microchip Technology Inc. DS22196A-page 5 Document Outline 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings † 1.2 Test Circuits FIGURE 1-1: AC and DC Test Circuit for Most Specifications. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V. FIGURE 2-4: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 2.2V. FIGURE 2-5: Input Offset Voltage vs. Output Voltage. FIGURE 2-6: Input Offset Voltage vs. Power Supply Voltage with VCM = VCMR_L. FIGURE 2-7: Input Offset Voltage vs. Power Supply Voltage with VCM = VCMR_H. FIGURE 2-8: Input Noise Voltage Density vs. Frequency. FIGURE 2-9: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-10: CMRR, PSRR vs. Frequency. FIGURE 2-11: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-12: Common Mode Input Voltage Headroom vs. Ambient Temperature. FIGURE 2-13: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-14: Input Bias Current vs. Common Mode Input Voltage. FIGURE 2-15: Quiescent Current vs Ambient Temperature. FIGURE 2-16: Quiescent Current vs. Power Supply Voltage. FIGURE 2-17: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-18: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage with VDD = 5.5V. FIGURE 2-19: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage with VDD = 2.2V. FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 5.5V. FIGURE 2-21: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature with VDD = 2.2V. FIGURE 2-22: Ouput Short Circuit Current vs. Power Supply Voltage. FIGURE 2-23: Output Voltage Swing vs. Frequency. FIGURE 2-24: Output Voltage Headroom vs. Output Current. FIGURE 2-25: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-26: Slew Rate vs. Ambient Temperature. FIGURE 2-27: Small Signal Non-Inverting Pulse Response. FIGURE 2-28: Small Signal Inverting Pulse Response. FIGURE 2-29: Large Signal Non-Inverting Pulse Response. FIGURE 2-30: Large Signal Inverting Pulse Response. FIGURE 2-31: The MCP6286 Shows No Phase Reversal. FIGURE 2-32: Closed Loop Output Impedance vs. Frequency. FIGURE 2-33: Measured Input Current vs. Input Voltage (below VSS). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Output 3.2 Analog Inputs 3.3 Power Supply Pins 4.0 Application Information 4.1 Input FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-3: Output Resistor, RISO Stabilizes Large Capacitive Loads. FIGURE 4-4: Recommended RISO Values for Capacitive Loads. 4.4 Supply Bypass 4.5 PCB Surface Leakage FIGURE 4-5: Example Guard Ring Layout for Inverting Gain. 4.6 Application Circuits FIGURE 4-6: Second-Order, Low-Pass Butterworth Filter with Sallen-Key Topology. FIGURE 4-7: Second-Order, Low-Pass Butterwork Filter with Multiple-Feedback Topology. FIGURE 4-8: Photovoltaic Mode Detector. FIGURE 4-9: Photoconductive Mode Detector. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Circuit Designer & Simulator 5.4 Microchip Advanced Part Selector (MAPS) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information