Datasheet ADA4817-1, ADA4817-2 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | Dual, Low Noise, 1 GHz FastFET Op Amplifier |
| Pages / Page | 25 / 6 — ADA4817-1/ADA4817-2. Data Sheet. PIN CONFIGURATIONS AND FUNCTION … |
| Revision | G |
| File Format / Size | PDF / 632 Kb |
| Document Language | English |
ADA4817-1/ADA4817-2. Data Sheet. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. ADA4817-1. TOP VIEW. (Not to Scale). PD 1. 8 +VS. FB 2
Text Version of Document
ADA4817-1/ADA4817-2 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADA4817-1 TOP VIEW (Not to Scale) PD 1 8 +VS FB 2 7 OUT –IN 3 6 NIC +IN 4 5 –VS NOTES 1. NIC = NO INTERNAL CONNECTION. 2. EXPOSED PAD CAN BE CONNECTED
5 00
TO GROUND PLANE OR NEGATIVE
6- 75
SUPPLY PLANE.
07 Figure 5. ADA4817-1 Pin Configuration (8-Lead LFCSP)
Table 5. ADA4817-1 Pi n Function Descriptions (8-Lead LFCSP) Pin No. Mnemonic Description
1 PD Power-Down. Do not leave floating. 2 FB Feedback Pin. 3 −IN Inverting Input. 4 +IN Noninverting Input. 5 −VS Negative Supply. 6 NIC No Internal Connection. 7 OUT Output. 8 +VS Positive Supply. Exposed pad (EPAD) Exposed Pad. Can be connected to GND, −VS plane, or left floating.
ADA4817-1 TOP VIEW (Not to Scale) FB 1 8 PD –IN 2 7 +VS +IN 3 6 OUT –VS 4 5 NIC NOTES 1. NIC = NO INTERNAL CONNECTION.
6 00
2. EXPOSED PAD. CAN BE CONNECTED TO GND,
6-
−VS PLANE, OR LEFT FLOATING.
775 0 Figure 6. ADA4817-1 Pin Configuration (8-Lead SOIC)
Table 6. ADA4817-1 Pi n Function Descriptions (8-Lead SOIC) Pin No. Mnemonic Description
1 FB Feedback Pin. 2 −IN Inverting Input. 3 +IN Noninverting Input. 4 −VS Negative Supply. 5 NIC No Internal Connection. 6 OUT Output. 7 +VS Positive Supply. 8 PD Power-Down. Do not leave floating. Exposed pad (EPAD) Exposed Pad. Can be connected to GND, −VS plane, or left floating. Rev. C | Page 6 of 25 Document Outline FEATURES APPLICATIONS CONNECTION DIAGRAMS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ±5 V OPERATION 5 V OPERATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM SAFE POWER DISSIPATION ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS THEORY OF OPERATION CLOSED-LOOP FREQUENCY RESPONSE NONINVERTING CLOSED-LOOP FREQUENCY RESPONSE INVERTING CLOSED-LOOP FREQUENCY RESPONSE WIDEBAND OPERATION DRIVING CAPACITIVE LOADS THERMAL CONSIDERATIONS POWER-DOWN OPERATION CAPACITIVE FEEDBACK HIGHER FREQUENCY ATTENUATION LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS SIGNAL ROUTING POWER SUPPLY BYPASSING GROUNDING EXPOSED PADDLE LEAKAGE CURRENTS INPUT CAPACITANCE INPUT-TO-INPUT/OUTPUT COUPLING APPLICATIONS INFORMATION LOW DISTORTION PINOUT WIDEBAND PHOTODIODE PREAMP HIGH SPEED JFET INPUT INSTRUMENTATION AMPLIFIER ACTIVE LOW-PASS FILTER (LPF) OUTLINE DIMENSIONS ORDERING GUIDE
5 00
TO GROUND PLANE OR NEGATIVE
6- 75
SUPPLY PLANE.
07 Figure 5. ADA4817-1 Pin Configuration (8-Lead LFCSP)
Table 5. ADA4817-1 Pi n Function Descriptions (8-Lead LFCSP) Pin No. Mnemonic Description
1 PD Power-Down. Do not leave floating. 2 FB Feedback Pin. 3 −IN Inverting Input. 4 +IN Noninverting Input. 5 −VS Negative Supply. 6 NIC No Internal Connection. 7 OUT Output. 8 +VS Positive Supply. Exposed pad (EPAD) Exposed Pad. Can be connected to GND, −VS plane, or left floating.
ADA4817-1 TOP VIEW (Not to Scale) FB 1 8 PD –IN 2 7 +VS +IN 3 6 OUT –VS 4 5 NIC NOTES 1. NIC = NO INTERNAL CONNECTION.
6 00
2. EXPOSED PAD. CAN BE CONNECTED TO GND,
6-
−VS PLANE, OR LEFT FLOATING.
775 0 Figure 6. ADA4817-1 Pin Configuration (8-Lead SOIC)
Table 6. ADA4817-1 Pi n Function Descriptions (8-Lead SOIC) Pin No. Mnemonic Description
1 FB Feedback Pin. 2 −IN Inverting Input. 3 +IN Noninverting Input. 4 −VS Negative Supply. 5 NIC No Internal Connection. 6 OUT Output. 7 +VS Positive Supply. 8 PD Power-Down. Do not leave floating. Exposed pad (EPAD) Exposed Pad. Can be connected to GND, −VS plane, or left floating. Rev. C | Page 6 of 25 Document Outline FEATURES APPLICATIONS CONNECTION DIAGRAMS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ±5 V OPERATION 5 V OPERATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM SAFE POWER DISSIPATION ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS THEORY OF OPERATION CLOSED-LOOP FREQUENCY RESPONSE NONINVERTING CLOSED-LOOP FREQUENCY RESPONSE INVERTING CLOSED-LOOP FREQUENCY RESPONSE WIDEBAND OPERATION DRIVING CAPACITIVE LOADS THERMAL CONSIDERATIONS POWER-DOWN OPERATION CAPACITIVE FEEDBACK HIGHER FREQUENCY ATTENUATION LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS SIGNAL ROUTING POWER SUPPLY BYPASSING GROUNDING EXPOSED PADDLE LEAKAGE CURRENTS INPUT CAPACITANCE INPUT-TO-INPUT/OUTPUT COUPLING APPLICATIONS INFORMATION LOW DISTORTION PINOUT WIDEBAND PHOTODIODE PREAMP HIGH SPEED JFET INPUT INSTRUMENTATION AMPLIFIER ACTIVE LOW-PASS FILTER (LPF) OUTLINE DIMENSIONS ORDERING GUIDE
