Datasheet LTC2165, LTC2164, LTC2163 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | 16-Bit, 125Msps Low Power ADCs |
| Pages / Page | 36 / 1 — FeaTures. DescripTion. applicaTions. Typical applicaTion. 2-Tone FFT, fIN … |
| File Format / Size | PDF / 684 Kb |
| Document Language | English |
FeaTures. DescripTion. applicaTions. Typical applicaTion. 2-Tone FFT, fIN = 70MHz and 69MHz
Model Line for this Datasheet
- LTC2163CUK#PBF LTC2163CUK#PBF LTC2163CUK#TRPBF LTC2163CUK#TRPBF LTC2163IUK#PBF LTC2163IUK#PBF LTC2163IUK#TRPBF LTC2163IUK#TRPBF
Text Version of Document
LTC2165/LTC2164/LTC2163 16-Bit, 125/105/80Msps Low Power ADCs
FeaTures DescripTion
n 76.8dB SNR The LTC®2165/LTC2164/LTC2163 are sampling 16-bit A/D n 90dB SFDR converters designed for digitizing high frequency, wide n Low Power: 194mW/163mW/108mW dynamic range signals. They are perfect for demanding n Single 1.8V Supply communications applications with AC performance that n CMOS, DDR CMOS, or DDR LVDS Outputs includes 76.8dB SNR and 90dB spurious free dynamic n Selectable Input Ranges: 1V range (SFDR). Ultralow jitter of 0.07ps P-P to 2VP-P RMS allows unders- n 550MHz Full Power Bandwidth S/H ampling of IF frequencies with excellent noise performance. n Optional Data Output Randomizer DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ) n Optional Clock Duty Cycle Stabilizer and no missing codes over temperature. The transition n Shutdown and Nap Modes noise is 3.4LSBRMS. n Serial SPI Port for Configuration n 48-Pin (7mm × 7mm) QFN Package The digital outputs can be either full rate CMOS, double data rate CMOS, or double data rate LVDS. A separate output power supply allows the CMOS output swing to
applicaTions
range from 1.2V to 1.8V. n Communications The ENC+ and ENC– inputs may be driven differentially n Cellular Base Stations or single-ended with a sine wave, PECL, LVDS, TTL, or n Software Defined Radios CMOS inputs. An optional clock duty cycle stabilizer al- n Portable Medical Imaging lows high performance at full speed for a wide range of n Multichannel Data Acquisition clock duty cycles. n Nondestructive Testing L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion 2-Tone FFT, fIN = 70MHz and 69MHz
1.8V 1.8V V OV 0 DD DD –10 –20 –30 ANALOG 16-BIT –40 S/H INPUT ADC CORE D15 –50 • CMOS, DDR –60 OUTPUT • CMOS OR DDR LVDS –70 DRIVERS • OUTPUTS AMPLITUDE (dBFS) –80 D0 –90 125MHz CLOCK –100 CONTROL CLOCK –110 –120 0 10 20 30 40 50 60 FREQUENCY (MHz) 2165 TA01b 2165 TA01a GND OGND 216543f 1 Document Outline Features Applications Description Absolute Maximum Ratings Typical Application Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Electrical Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts
FeaTures DescripTion
n 76.8dB SNR The LTC®2165/LTC2164/LTC2163 are sampling 16-bit A/D n 90dB SFDR converters designed for digitizing high frequency, wide n Low Power: 194mW/163mW/108mW dynamic range signals. They are perfect for demanding n Single 1.8V Supply communications applications with AC performance that n CMOS, DDR CMOS, or DDR LVDS Outputs includes 76.8dB SNR and 90dB spurious free dynamic n Selectable Input Ranges: 1V range (SFDR). Ultralow jitter of 0.07ps P-P to 2VP-P RMS allows unders- n 550MHz Full Power Bandwidth S/H ampling of IF frequencies with excellent noise performance. n Optional Data Output Randomizer DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ) n Optional Clock Duty Cycle Stabilizer and no missing codes over temperature. The transition n Shutdown and Nap Modes noise is 3.4LSBRMS. n Serial SPI Port for Configuration n 48-Pin (7mm × 7mm) QFN Package The digital outputs can be either full rate CMOS, double data rate CMOS, or double data rate LVDS. A separate output power supply allows the CMOS output swing to
applicaTions
range from 1.2V to 1.8V. n Communications The ENC+ and ENC– inputs may be driven differentially n Cellular Base Stations or single-ended with a sine wave, PECL, LVDS, TTL, or n Software Defined Radios CMOS inputs. An optional clock duty cycle stabilizer al- n Portable Medical Imaging lows high performance at full speed for a wide range of n Multichannel Data Acquisition clock duty cycles. n Nondestructive Testing L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion 2-Tone FFT, fIN = 70MHz and 69MHz
1.8V 1.8V V OV 0 DD DD –10 –20 –30 ANALOG 16-BIT –40 S/H INPUT ADC CORE D15 –50 • CMOS, DDR –60 OUTPUT • CMOS OR DDR LVDS –70 DRIVERS • OUTPUTS AMPLITUDE (dBFS) –80 D0 –90 125MHz CLOCK –100 CONTROL CLOCK –110 –120 0 10 20 30 40 50 60 FREQUENCY (MHz) 2165 TA01b 2165 TA01a GND OGND 216543f 1 Document Outline Features Applications Description Absolute Maximum Ratings Typical Application Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Electrical Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts
