Datasheet LTC2261-14, LTC2260-14, LTC2259-14 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 14-Bit, 125Msps Ultra-Low Power 1.8V ADCs |
| Pages / Page | 34 / 8 — TiMing DiagraMs. Double-Data Rate CMOS Output Mode Timing. All Outputs … |
| File Format / Size | PDF / 809 Kb |
| Document Language | English |
TiMing DiagraMs. Double-Data Rate CMOS Output Mode Timing. All Outputs Are Single Ended and Have CMOS Levels
Model Line for this Datasheet
- LTC2259CUJ-14#PBF LTC2259CUJ-14#PBF LTC2259CUJ-14#TRPBF LTC2259CUJ-14#TRPBF LTC2259IUJ-14#PBF LTC2259IUJ-14#PBF LTC2259IUJ-14#TRPBF LTC2259IUJ-14#TRPBF
Text Version of Document
LTC2261-14 LTC2260-14/LTC2259-14
TiMing DiagraMs Double-Data Rate CMOS Output Mode Timing All Outputs Are Single Ended and Have CMOS Levels
tAP ANALOG N N + 2 N + 4 INPUT N + 3 tH N + 1 tL ENC– ENC+ tD tD D0_1 D0N-5 D1N-5 D0N-4 D1N-4 D0N-3 D1N-3 D0N-2 D1N-2 ••• D12_13 D12N-5 D13N-5 D12N-4 D13N-4 D12N-3 D13N-3 D12N-2 D13N-2 OF OFN-5 OFN-4 OFN-3 OFN-2 tC tC CLKOUT+ CLKOUT– 226114 TD02
Double-Data Rate LVDS Output Mode Timing All Outputs Are Differential and Have LVDS Levels
tAP ANALOG N N + 2 N + 4 INPUT N + 3 tH N + 1 tL ENC– ENC+ tD tD D0_1+ D0N-5 D1N-5 D0N-4 D1N-4 D0N-3 D1N-3 D0N-2 D1N-2 D0_1– ••• D12_13+ D12N-5 D13N-5 D12N-4 D13N-4 D12N-3 D13N-3 D12N-2 D13N-2 D12_13– OF+ OFN-5 OFN-4 OFN-3 OFN-3 OF– tC tC CLKOUT+ CLKOUT– 226114 TD03 226114fc 8 For more information www.linear.com/LTC2261-14 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configurations Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
TiMing DiagraMs Double-Data Rate CMOS Output Mode Timing All Outputs Are Single Ended and Have CMOS Levels
tAP ANALOG N N + 2 N + 4 INPUT N + 3 tH N + 1 tL ENC– ENC+ tD tD D0_1 D0N-5 D1N-5 D0N-4 D1N-4 D0N-3 D1N-3 D0N-2 D1N-2 ••• D12_13 D12N-5 D13N-5 D12N-4 D13N-4 D12N-3 D13N-3 D12N-2 D13N-2 OF OFN-5 OFN-4 OFN-3 OFN-2 tC tC CLKOUT+ CLKOUT– 226114 TD02
Double-Data Rate LVDS Output Mode Timing All Outputs Are Differential and Have LVDS Levels
tAP ANALOG N N + 2 N + 4 INPUT N + 3 tH N + 1 tL ENC– ENC+ tD tD D0_1+ D0N-5 D1N-5 D0N-4 D1N-4 D0N-3 D1N-3 D0N-2 D1N-2 D0_1– ••• D12_13+ D12N-5 D13N-5 D12N-4 D13N-4 D12N-3 D13N-3 D12N-2 D13N-2 D12_13– OF+ OFN-5 OFN-4 OFN-3 OFN-3 OF– tC tC CLKOUT+ CLKOUT– 226114 TD03 226114fc 8 For more information www.linear.com/LTC2261-14 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configurations Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
