Datasheet LTC2471, LTC2473 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Selectable 208sps/833sps, 16-Bit I2C ΔΣ ADCs with 10ppm/°C Max Precision Reference |
| Pages / Page | 20 / 10 — applicaTions inForMaTion. Data Transferring. The START and STOP … |
| File Format / Size | PDF / 496 Kb |
| Document Language | English |
applicaTions inForMaTion. Data Transferring. The START and STOP Conditions. Output Data Format
Model Line for this Datasheet
Text Version of Document
LTC2471/LTC2473
applicaTions inForMaTion
The LTC2471/LTC2473 can only be addressed as a slave.
Data Transferring
It can only transmit the last conversion result. The serial After the START condition, the I2C bus is busy and data clock line, SCL, is always an input to the LTC2471/LTC2473 transfer can begin between the master and the addressed and the serial data line SDA is bidirectional. Figure 5 shows slave. Data is transferred over the bus in groups of nine the definition of the I2C timing. bits, one byte followed by one acknowledge (ACK) bit. The
The START and STOP Conditions
master releases the SDA line during the ninth SCL clock cycle. The slave device can issue an ACK by pulling SDA A START (S) condition is generated by transitioning SDA LOW or issue a Not Acknowledge (NACK) by leaving the from HIGH to LOW while SCL is HIGH. The bus is consid- SDA line HIGH impedance (the external pull-up resistor ered to be busy after the START condition. When the data will hold the line HIGH). Change of data only occurs while transfer is finished, a STOP (P) condition is generated by the clock line (SCL) is LOW. transitioning SDA from LOW to HIGH while SCL is HIGH.
Output Data Format
The bus is free after a STOP is generated. START and STOP conditions are always generated by the master. After a START condition, the master sends a 7-bit address followed by a read request (R) bit. The bit R is 1 for a When the bus is in use, it stays busy if a repeated START Read Request. If the 7-bit address matches the LTC2471/ (Sr) is generated instead of a STOP condition. The repeated LTC2473’s address (0010100 or 1010100, depending on START timing is functionally identical to the START and the state of the pin A0) the ADC is selected. When the is used for reading from the device before the initiation device is addressed during the conversion state, it does of a new conversion. SDA t t SU(DAT) tf t r tr LOW tf tHD(SDA) tSP tBUF SCL tHD(STA) tSU(STA) tSU(STO) S tHD(DAT) tHIGH Sr P S 24713 F05
Figure 5. Definition of Timing for Fast/Standard Mode Devices on the I2C Bus
24713fb 10 For more information www.linear.com/LTC2471 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Analog Inputs Power Requirements I2C Inputs and Outputs I2C Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Package Description Revision History Typical Application Related Parts
applicaTions inForMaTion
The LTC2471/LTC2473 can only be addressed as a slave.
Data Transferring
It can only transmit the last conversion result. The serial After the START condition, the I2C bus is busy and data clock line, SCL, is always an input to the LTC2471/LTC2473 transfer can begin between the master and the addressed and the serial data line SDA is bidirectional. Figure 5 shows slave. Data is transferred over the bus in groups of nine the definition of the I2C timing. bits, one byte followed by one acknowledge (ACK) bit. The
The START and STOP Conditions
master releases the SDA line during the ninth SCL clock cycle. The slave device can issue an ACK by pulling SDA A START (S) condition is generated by transitioning SDA LOW or issue a Not Acknowledge (NACK) by leaving the from HIGH to LOW while SCL is HIGH. The bus is consid- SDA line HIGH impedance (the external pull-up resistor ered to be busy after the START condition. When the data will hold the line HIGH). Change of data only occurs while transfer is finished, a STOP (P) condition is generated by the clock line (SCL) is LOW. transitioning SDA from LOW to HIGH while SCL is HIGH.
Output Data Format
The bus is free after a STOP is generated. START and STOP conditions are always generated by the master. After a START condition, the master sends a 7-bit address followed by a read request (R) bit. The bit R is 1 for a When the bus is in use, it stays busy if a repeated START Read Request. If the 7-bit address matches the LTC2471/ (Sr) is generated instead of a STOP condition. The repeated LTC2473’s address (0010100 or 1010100, depending on START timing is functionally identical to the START and the state of the pin A0) the ADC is selected. When the is used for reading from the device before the initiation device is addressed during the conversion state, it does of a new conversion. SDA t t SU(DAT) tf t r tr LOW tf tHD(SDA) tSP tBUF SCL tHD(STA) tSU(STA) tSU(STO) S tHD(DAT) tHIGH Sr P S 24713 F05
Figure 5. Definition of Timing for Fast/Standard Mode Devices on the I2C Bus
24713fb 10 For more information www.linear.com/LTC2471 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Analog Inputs Power Requirements I2C Inputs and Outputs I2C Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Package Description Revision History Typical Application Related Parts
