Datasheet AD7091R-2, AD7091R-4, AD7091R-8 (Analog Devices) - 5

ManufacturerAnalog Devices
Description8-Channel, 1 MSPS, Ultralow Power, 12-Bit ADC in 24-Lead TSSOP
Pages / Page42 / 5 — Data Sheet. AD7091R-2/AD7091R-4/AD7091R-8. TIMING SPECIFICATIONS. Table …
RevisionC
File Format / SizePDF / 875 Kb
Document LanguageEnglish

Data Sheet. AD7091R-2/AD7091R-4/AD7091R-8. TIMING SPECIFICATIONS. Table 2. Parameter Symbol. Min. Typ. Max. Unit. 500µA. Y% V. X% V. DRIVE

Data Sheet AD7091R-2/AD7091R-4/AD7091R-8 TIMING SPECIFICATIONS Table 2 Parameter Symbol Min Typ Max Unit 500µA Y% V X% V DRIVE

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Data Sheet AD7091R-2/AD7091R-4/AD7091R-8 TIMING SPECIFICATIONS
VDD = 2.7 V to 5.25 V, VDRIVE = 1.8 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.
Table 2. Parameter Symbol Min Typ Max Unit
Conversion Time: CONVST Falling Edge to Data Available tCONVERT 600 ns Acquisition Time tACQ 400 ns Time Between Conversions (Normal Mode) tCYC 1000 ns CONVST Pulse Width tCNVPW 10 500 ns SCLK Period (Normal Mode) tSCLK VDRIVE Above 2.7 V 16 ns VDRIVE Above 1.8 V 22 ns SCLK Period (Chain Mode) tSCLK VDRIVE Above 2.7 V 20 ns VDRIVE Above 1.8 V 25 ns SCLK Low Time tSCLKL 6 ns SCLK High Time tSCLKH 6 ns SCLK Falling Edge to Data Remains Valid tHSDO 5 ns SCLK Falling Edge to Data Valid Delay tDSDO VDRIVE Above 4.5 V 12 ns VDRIVE Above 3.3 V 13 ns VDRIVE Above 2.7 V 14 ns VDRIVE Above 1.8 V 20 ns End of Conversion to CS Falling Edge tEOCCSL 5 ns CS Low to SDO Enabled tEN 5 ns CS High or Last SCLK Falling Edge to SDO High Impedance tDIS 5 ns SDI Data Setup Time Prior to SCLK Rising Edge tSSDISCLK 5 ns SDI Data Hold Time After SCLK Rising Edge tHSDISCLK 2 ns Last SCLK Falling Edge to Next CONVST Falling Edge tQUIET 50 ns RESET Pulse Width tRESETPW 10 ns RESET Pulse Delay Upon Power Up tRESET_DELAY 50 ns Time Between Conversions (Power On Software Reset) tCYC_RESET 2 μs
500µA I Y% V OL X% V DRIVE DRIVE tDELAY tDELAY 2 TO SDO 1.4V VIH V 2 IH C 2 V 2 V L IL IL 20pF NOTES 1FOR V ≤ 3.0V, X = 90 AND Y = 10; FOR > 3.0V, X = 70 AND Y = 30. DRIVE VDRIVE 500µA I
138 139
OH 2MINIMUM VIHAND MAXIMUM VIL USED. SEE SPECIFICATIONS FOR DIGITAL
91- 10891-
INPUTS PARAMETER IN TABLE 2.
108 Figure 2. Load Circuit for Digital Interface Timing Figure 3. Voltage Levels for Timing Rev. C | Page 5 of 42 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION REFERENCE POWER SUPPLY DEVICE RESET TYPICAL CONNECTION DIAGRAM ANALOG INPUT DRIVER AMPLIFIER CHOICE REGISTERS ADDRESSING REGISTERS CONVERSION RESULT REGISTER CHANNEL REGISTER CONFIGURATION REGISTER ALERT INDICATION REGISTER CHANNEL x LOW LIMIT REGISTER CHANNEL x HIGH LIMIT REGISTER CHANNEL x HYSTERESIS REGISTER SERIAL PORT INTERFACE READING CONVERSION RESULT WRITING DATA TO THE REGISTERS READING DATA FROM THE REGISTERS POWER-ON DEVICE INITIALIZATION MODES OF OPERATION NORMAL MODE POWER-DOWN MODE ALERT (AD7091R-4 AND AD7091R-8 ONLY) BUSY (AD7091R-4 AND AD7091R-8 ONLY) CHANNEL SEQUENCER DAISY CHAIN OUTLINE DIMENSIONS ORDERING GUIDE
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