Datasheet AD7192 (Analog Devices) - 5

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AD7192 Parameter AD7192B Unit Test Conditions/Comments1
External Clock @ 50 Hz, 60 Hz 120 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 82 dB min 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz. @ 50 Hz 120 dB min 50 Hz output data rate, 50 ± 1 Hz. @ 60 Hz 120 dB min 60 Hz output data rate, 60 ± 1 Hz. Sinc3 Filter Internal Clock @ 50 Hz, 60 Hz 75 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 60 dB min 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz. @ 50 Hz 70 dB min 50 Hz output data rate, 50 ± 1 Hz. @ 60 Hz 70 dB min 60 Hz output data rate, 60 ± 1 Hz. External Clock @ 50 Hz, 60 Hz 100 dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 67 dB min 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz. @ 50 Hz 95 dB min 50 Hz output data rate, 50 ± 1 Hz. @ 60 Hz 95 dB min 60 Hz output data rate, 60 ± 1 Hz. ANALOG INPUTS Differential Input Voltage Ranges ± VREF/gain V nom VREF = REFINx(+) − REFINx(−), gain = 1 to 128. ± (AVDD – 1.25 V)/gain V min/max Gain > 1. Absolute AIN Voltage Limits2 Unbuffered Mode AGND − 50 mV V min AVDD + 50 mV V max Buffered Mode AGND + 250 mV V min AVDD − 250 mV V max Analog Input Current Buffered Mode Input Current2 ±2 nA max Gain = 1. ±3 nA max Gain > 1. Input Current Drift ±5 pA/°C typ Unbuffered Mode Input Current ±3.5 μA/V typ Gain = 1, input current varies with input voltage. ±1 μA/V typ Gain > 1. Input Current Drift ±0.05 nA/V/°C typ External clock. ±1.6 nA/V/°C typ Internal clock. REFERENCE INPUT REFIN Voltage AVDD V nom REFIN = REFINx(+) − REFINx(−). 1 V min AVDD V max The differential input must be limited to ±(AVDD – 1.25 V)/gain when gain > 1. Absolute REFIN Voltage Limits2 GND – 50 mV V min AVDD + 50 mV V max Average Reference Input Current 4.5 μA/V typ Rev. A | Page 4 of 40 Document Outline FEATURES INTERFACE APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS CIRCUIT AND TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS RMS NOISE AND RESOLUTION SINC4 CHOP DISABLED SINC3 CHOP DISABLED SINC4 CHOP ENABLED SINC3 CHOP ENABLED ON-CHIP REGISTERS COMMUNICATIONS REGISTER STATUS REGISTER MODE REGISTER CONFIGURATION REGISTER DATA REGISTER ID REGISTER GPOCON REGISTER OFFSET REGISTER FULL-SCALE REGISTER ADC CIRCUIT INFORMATION OVERVIEW FILTER, OUTPUT DATA RATE, AND SETTLING TIME Chop Disabled Chop Enabled 50 Hz/60Hz Rejection Zero Latency Channel Sequencer Single Conversion Mode Continuous Conversion Mode Continuous Read CIRCUIT DESCRIPTION ANALOG INPUT CHANNEL PROGRAMMABLE GAIN ARRAY (PGA) BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING CLOCK BURNOUT CURRENTS REFERENCE REFERENCE DETECT RESET SYSTEM SYNCHRONIZATION TEMPERATURE SENSOR BRIDGE POWER-DOWN SWITCH LOGIC OUTPUTS ENABLE PARITY CALIBRATION GROUNDING AND LAYOUT APPLICATIONS INFORMATION WEIGH SCALES OUTLINE DIMENSIONS ORDERING GUIDE