Datasheet AD7765 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | 24-Bit, 156 kSPS, 112 dB Sigma-Delta ADC with On-Chip Buffers and Serial Interface |
| Pages / Page | 33 / 3 — AD7765. TABLE OF CONTENTS. REVISION HISTORY 8/09—Rev. 0 to Rev. A. … |
| Revision | C |
| File Format / Size | PDF / 896 Kb |
| Document Language | English |
AD7765. TABLE OF CONTENTS. REVISION HISTORY 8/09—Rev. 0 to Rev. A. 6/07—Revision 0: Initial Version
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AD7765 TABLE OF CONTENTS
Features .. 1 AD7765 Functionality ... 21 Applications ... 1 Synchronization .. 21 General Description ... 1 Overrange Alerts .. 21 Functional Block Diagram .. 1 Power Modes ... 22 Revision History ... 2 Decimation Rate Pin .. 22 Specifications ... 3 Daisy Chaining ... 23 Timing Specifications .. 6 Reading Data in Daisy-Chain Mode ... 23 Timing Diagrams .. 7 Writing Data in Daisy-Chain Mode .. 24 Absolute Maximum Ratings .. 8 Clocking the AD7765 .. 25 ESD Caution .. 8 MCLK Jitter Requirements ... 25 Pin Configuration and Function Descriptions ... 9 Decoupling and Layout Information ... 26 Typical Performance Characteristics ... 11 Supply Decoupling ... 26 Terminology .. 14 Reference Voltage Filtering ... 26 Theory of Operation .. 15 Differential Amplifier Components .. 26 Σ-Δ Modulation and Digital Filtering .. 15 Layout Considerations ... 26 AD7765 Antialias Protection .. 16 Using the AD7765 .. 27 AD7765 Input Structure .. 17 Bias Resistor Selection ... 27 On-Chip Differential Amplifier ... 18 AD7765 Registers ... 28 Modulator Input Structure .. 19 Control Register ... 28 Driving the Modulator Inputs Directly ... 19 Status Register ... 28 AD7765 Interface .. 20 Gain Register—Address 0x0004 ... 29 Reading Data ... 20 Overrange Register—Address 0x0005 ... 29 Reading Status and Other Registers ... 20 Outline Dimensions ... 30 Writing to the AD7765 .. 20 Ordering Guide .. 30
REVISION HISTORY 8/09—Rev. 0 to Rev. A
Changes to Table 3 .. 6
Changes to Table 4 .. 8 Changes to Σ-Δ Modulation and Digital Filtering Section ... 15
Added AD7765 Antialias Protection Section ... 16
Added Driving the Modulator Inputs Directly Section .. 19
Changes to Synchronization Section, Added Figure 35 .. 21 Changes to Power Modes Section, Added RESET/PWRDWN
Mode Section, Added Figure 38 ... 22
Changes to Daisy Chaining Section ... 23 Changes to Using the AD7765 Section .. 27
6/07—Revision 0: Initial Version
Rev. A | Page 2 of 32 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Σ-Δ Modulation and Digital Filtering AD7765 Antialias Protection AD7765 Input Structure On-Chip Differential Amplifier Modulator Input Structure Driving the Modulator Inputs Directly AD7765 Interface Reading Data Reading Status and Other Registers Writing to the AD7765 AD7765 Functionality Synchronization Overrange Alerts Power Modes Low Power Mode RESET/PWRDWN Mode Decimation Rate Pin Daisy Chaining Reading Data in Daisy-Chain Mode Writing Data in Daisy-Chain Mode Clocking the AD7765 MCLK Jitter Requirements Example 1 Example 2 Decoupling and Layout Information Supply Decoupling Reference Voltage Filtering Differential Amplifier Components Layout Considerations Using the AD7765 Bias Resistor Selection AD7765 Registers Control Register Status Register Gain Register—Address 0x0004 Non-Bit-Mapped, Default Value 0xA000 Overrange Register—Address 0x0005 Non-Bit-Mapped, Default Value 0xCCCC Outline Dimensions Ordering Guide
AD7765 TABLE OF CONTENTS
Features .. 1 AD7765 Functionality ... 21 Applications ... 1 Synchronization .. 21 General Description ... 1 Overrange Alerts .. 21 Functional Block Diagram .. 1 Power Modes ... 22 Revision History ... 2 Decimation Rate Pin .. 22 Specifications ... 3 Daisy Chaining ... 23 Timing Specifications .. 6 Reading Data in Daisy-Chain Mode ... 23 Timing Diagrams .. 7 Writing Data in Daisy-Chain Mode .. 24 Absolute Maximum Ratings .. 8 Clocking the AD7765 .. 25 ESD Caution .. 8 MCLK Jitter Requirements ... 25 Pin Configuration and Function Descriptions ... 9 Decoupling and Layout Information ... 26 Typical Performance Characteristics ... 11 Supply Decoupling ... 26 Terminology .. 14 Reference Voltage Filtering ... 26 Theory of Operation .. 15 Differential Amplifier Components .. 26 Σ-Δ Modulation and Digital Filtering .. 15 Layout Considerations ... 26 AD7765 Antialias Protection .. 16 Using the AD7765 .. 27 AD7765 Input Structure .. 17 Bias Resistor Selection ... 27 On-Chip Differential Amplifier ... 18 AD7765 Registers ... 28 Modulator Input Structure .. 19 Control Register ... 28 Driving the Modulator Inputs Directly ... 19 Status Register ... 28 AD7765 Interface .. 20 Gain Register—Address 0x0004 ... 29 Reading Data ... 20 Overrange Register—Address 0x0005 ... 29 Reading Status and Other Registers ... 20 Outline Dimensions ... 30 Writing to the AD7765 .. 20 Ordering Guide .. 30
REVISION HISTORY 8/09—Rev. 0 to Rev. A
Changes to Table 3 .. 6
Changes to Table 4 .. 8 Changes to Σ-Δ Modulation and Digital Filtering Section ... 15
Added AD7765 Antialias Protection Section ... 16
Added Driving the Modulator Inputs Directly Section .. 19
Changes to Synchronization Section, Added Figure 35 .. 21 Changes to Power Modes Section, Added RESET/PWRDWN
Mode Section, Added Figure 38 ... 22
Changes to Daisy Chaining Section ... 23 Changes to Using the AD7765 Section .. 27
6/07—Revision 0: Initial Version
Rev. A | Page 2 of 32 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Σ-Δ Modulation and Digital Filtering AD7765 Antialias Protection AD7765 Input Structure On-Chip Differential Amplifier Modulator Input Structure Driving the Modulator Inputs Directly AD7765 Interface Reading Data Reading Status and Other Registers Writing to the AD7765 AD7765 Functionality Synchronization Overrange Alerts Power Modes Low Power Mode RESET/PWRDWN Mode Decimation Rate Pin Daisy Chaining Reading Data in Daisy-Chain Mode Writing Data in Daisy-Chain Mode Clocking the AD7765 MCLK Jitter Requirements Example 1 Example 2 Decoupling and Layout Information Supply Decoupling Reference Voltage Filtering Differential Amplifier Components Layout Considerations Using the AD7765 Bias Resistor Selection AD7765 Registers Control Register Status Register Gain Register—Address 0x0004 Non-Bit-Mapped, Default Value 0xA000 Overrange Register—Address 0x0005 Non-Bit-Mapped, Default Value 0xCCCC Outline Dimensions Ordering Guide
