Datasheet AD7721 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | CMOS, 12-/16-Bit, 312.5 kHz/468.75 kHz Sigma-Delta ADC |
| Pages / Page | 17 / 3 — AD7721–SPECIFICATIONS1 (AVDD = +5 V. 5%; DVDD = +5 V. 5%; AGND = DGND = 0 … |
| Revision | A |
| File Format / Size | PDF / 299 Kb |
| Document Language | English |
AD7721–SPECIFICATIONS1 (AVDD = +5 V. 5%; DVDD = +5 V. 5%; AGND = DGND = 0 V,
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Text Version of Document
AD7721–SPECIFICATIONS1 (AVDD = +5 V
6
5%; DVDD = +5 V
6
5%; AGND = DGND = 0 V, fCLK = 15 MHz, REFIN = +2.5 V; TA = TMIN to TMAX, unless otherwise noted) Parameter A Version S Version Units Test Conditions/Comments SERIAL MODE ONLY
STATIC PERFORMANCE Resolution 16 16 Bits Minimum Resolution for Which 12 12 Bits min Guaranteed 12 Bits Monotonic No Missing Codes Is Guaranteed Differential Nonlinearity ±8 ±8 LSB typ Integral Nonlinearity ±16 ±16 LSB max 16-Bit Operation DC CMRR 70 70 dB min Bipolar Mode Offset Error2 Unipolar Mode ±3.66 ±3.66 mV max Typically 0.61 mV Bipolar Mode ±3.66 ±3.66 mV max Typically 0.61 mV Full-Scale Error 2, 3 Unipolar Mode ±4.88 ±4.88 mV max Typically 0.61 mV Bipolar Mode ±4.88 ±4.88 mV max Typically 1.22 mV Unipolar Offset Drift 0.05 0.05 mV/°C typ Bipolar Offset Drift 0.04 0.04 mV/°C typ ANALOG INPUTS Signal Input Span (VIN1–VIN2) Bipolar Mode ±VREFIN/2 ±VREFIN/2 Volts max UNI = VIH Unipolar Mode 0 to VREFIN 0 to VREFIN Volts max UNI = VIL Maximum Input Voltage AVDD AVDD Volts Minimum Input Voltage 0 0 Volts Input Sampling Capacitance 1.6 1.6 pF typ Input Sampling Rate 2 fCLK 2 fCLK MHz Guaranteed by Design Differential Input Impedance 20.8 20.8 kΩ typ With 15 MHz on CLK Pin REFERENCE INPUTS VREFIN 2.4 to 2.6 2.4 to 2.6 V min/V max REFIN Input Current 200 200 µA typ DYNAMIC SPECIFICATIONS Signal to (Noise + Distortion) 74 74 dB min Input Bandwidth 0 kHz to 210 kHz Total Harmonic Distortion –78 –78 dB max Input Bandwidth 0 kHz to 229.2 kHz Frequency Response 0 kHz–210 kHz ±0.05 ±0.05 dB max 229.2 kHz –3 –3 dB min 259.01 kHz to 14.74 MHz –72 –72 dB min CLOCK CLK Duty Ratio 45 to 55 45 to 55 % max For Specified Operation VCLKH, CLK High Voltage 0.7 × DVDD 0.7 × DVDD V min CLK Uses CMOS Logic VCLKL, CLK Low Voltage 0.3 × DVDD 0.3 × DVDD V max LOGIC INPUTS VINH, Input High Voltage 2.0 2.0 V min VINL, Input Low Voltage 0.8 0.8 V max IINH, Input Current 10 10 µA max CIN, Input Capacitance 10 10 pF max LOGIC OUTPUTS VOH, Output High Voltage 4.0 4.0 V min |IOUT| ≤ 200 µA VOL, Output Low Voltage 0.4 0.4 V max |IOUT| ≤ 1.6 mA POWER SUPPLIES AVDD 4.75/5.25 4.75/5.25 V min/V max DVDD 4.75/5.25 4.75/5.25 V min/V max IDD (Total from AVDD, DVDD) 28.5 28.5 mA max Digital Inputs Equal to 0 V or DVDD Power Consumption 150 150 mW max Active Mode Power Consumption 100 100 µW max Standby Mode NOTES 1Operating temperature range is as follows: A Version: –40°C to +85°C; S Version: –55°C to +125°C. 2Applies after calibration at temperature of interest. 3Full-scale error applies to both positive and negative full-scale error. The ADC gain is calibrated w.r.t. the voltage on the REFIN pin. Specifications subject to change without notice. –2– REV. A
6
5%; DVDD = +5 V
6
5%; AGND = DGND = 0 V, fCLK = 15 MHz, REFIN = +2.5 V; TA = TMIN to TMAX, unless otherwise noted) Parameter A Version S Version Units Test Conditions/Comments SERIAL MODE ONLY
STATIC PERFORMANCE Resolution 16 16 Bits Minimum Resolution for Which 12 12 Bits min Guaranteed 12 Bits Monotonic No Missing Codes Is Guaranteed Differential Nonlinearity ±8 ±8 LSB typ Integral Nonlinearity ±16 ±16 LSB max 16-Bit Operation DC CMRR 70 70 dB min Bipolar Mode Offset Error2 Unipolar Mode ±3.66 ±3.66 mV max Typically 0.61 mV Bipolar Mode ±3.66 ±3.66 mV max Typically 0.61 mV Full-Scale Error 2, 3 Unipolar Mode ±4.88 ±4.88 mV max Typically 0.61 mV Bipolar Mode ±4.88 ±4.88 mV max Typically 1.22 mV Unipolar Offset Drift 0.05 0.05 mV/°C typ Bipolar Offset Drift 0.04 0.04 mV/°C typ ANALOG INPUTS Signal Input Span (VIN1–VIN2) Bipolar Mode ±VREFIN/2 ±VREFIN/2 Volts max UNI = VIH Unipolar Mode 0 to VREFIN 0 to VREFIN Volts max UNI = VIL Maximum Input Voltage AVDD AVDD Volts Minimum Input Voltage 0 0 Volts Input Sampling Capacitance 1.6 1.6 pF typ Input Sampling Rate 2 fCLK 2 fCLK MHz Guaranteed by Design Differential Input Impedance 20.8 20.8 kΩ typ With 15 MHz on CLK Pin REFERENCE INPUTS VREFIN 2.4 to 2.6 2.4 to 2.6 V min/V max REFIN Input Current 200 200 µA typ DYNAMIC SPECIFICATIONS Signal to (Noise + Distortion) 74 74 dB min Input Bandwidth 0 kHz to 210 kHz Total Harmonic Distortion –78 –78 dB max Input Bandwidth 0 kHz to 229.2 kHz Frequency Response 0 kHz–210 kHz ±0.05 ±0.05 dB max 229.2 kHz –3 –3 dB min 259.01 kHz to 14.74 MHz –72 –72 dB min CLOCK CLK Duty Ratio 45 to 55 45 to 55 % max For Specified Operation VCLKH, CLK High Voltage 0.7 × DVDD 0.7 × DVDD V min CLK Uses CMOS Logic VCLKL, CLK Low Voltage 0.3 × DVDD 0.3 × DVDD V max LOGIC INPUTS VINH, Input High Voltage 2.0 2.0 V min VINL, Input Low Voltage 0.8 0.8 V max IINH, Input Current 10 10 µA max CIN, Input Capacitance 10 10 pF max LOGIC OUTPUTS VOH, Output High Voltage 4.0 4.0 V min |IOUT| ≤ 200 µA VOL, Output Low Voltage 0.4 0.4 V max |IOUT| ≤ 1.6 mA POWER SUPPLIES AVDD 4.75/5.25 4.75/5.25 V min/V max DVDD 4.75/5.25 4.75/5.25 V min/V max IDD (Total from AVDD, DVDD) 28.5 28.5 mA max Digital Inputs Equal to 0 V or DVDD Power Consumption 150 150 mW max Active Mode Power Consumption 100 100 µW max Standby Mode NOTES 1Operating temperature range is as follows: A Version: –40°C to +85°C; S Version: –55°C to +125°C. 2Applies after calibration at temperature of interest. 3Full-scale error applies to both positive and negative full-scale error. The ADC gain is calibrated w.r.t. the voltage on the REFIN pin. Specifications subject to change without notice. –2– REV. A
