Datasheet AD9142 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | Dual, 16-Bit, 1600 MSPS, TxDAC+ Digital-to-Analog Converter |
| Pages / Page | 65 / 4 — Data Sheet. AD9142. REVISION HISTORY 11/12—Revision 0: Initial Version |
| File Format / Size | PDF / 1.2 Mb |
| Document Language | English |
Data Sheet. AD9142. REVISION HISTORY 11/12—Revision 0: Initial Version
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Data Sheet AD9142
PLL Status Register ... 48 NCO_PHASE_OFFSET1 Register .. 55 IDAC FS Adjust LSB Register .. 48 IQ_PHASE_ADJ0 Register .. 55 IDAC FS Adjust MSB Register .. 48 IQ_PHASE_ADJ1 Register .. 55 QDAC FS Adjust LSB Register .. 48 IDAC_DC_OFFSET0 Register .. 55 QDAC FS Adjust MSB Register .. 49 IDAC_DC_OFFSET1 Register .. 55 Die Temperature Sensor Control Register ... 49 QDAC_DC_OFFSET0 Register .. 55 Die Temperature LSB Register .. 49 QDAC_DC_OFFSET1 Register .. 56 Die Temperature MSB Register ... 49 IDAC_GAIN_ADJ Register... 56 Chip ID Register .. 49 QDAC_GAIN_ADJ Register ... 56 Interrupt Configuation Register ... 50 Gain Step Control0 Register .. 56 Sync CTRL Register .. 50 Gain Step Control1 Register .. 56 Frame Reset CTRL Register ... 50 TX Enable Control Register .. 57 FIFO Level Configuration Register .. 51 DAC Output Control Register .. 57 FIFO Level Readback Register .. 51 Data Receiver Test Control Register ... 57 FIFO CTRL Register ... 51 Data Receiver Test Control Register ... 57 Data Format Select Register ... 52 Device Configuration0 Register .. 58 Datapath Control Register ... 52 Version Register .. 58 Interpolation Control Register .. 52 Device Configuration1 Register .. 58 Over Threshold CTRL0 Register .. 53 Device Configuration2 Register .. 58 Over Threshold CTRL1 Register .. 53 DAC Latency and System Skews ... 59 Over Threshold CTRL2 Register .. 53 DAC Latency Variations... 59 Input Power Readback LSB Register .. 53 FIFO Latency Variation .. 59 Input Power Readback MSB Register ... 53 Clock Generation Latency Variation .. 60 NCO Control Register .. 54 Correcting System Skews ... 60 NCO_FREQ_TUNING_WORD0 Register ... 54 Packaging and Ordering Information .. 61 NCO_FREQ_TUNING_WORD1 Register ... 54 Outline Dimensions.. 61 NCO_FREQ_TUNING_WORD2 Register ... 54 Ordering Guide ... 61 NCO_FREQ_TUNING_WORD3 Register ... 54 NCO_PHASE_OFFSET0 Register .. 54
REVISION HISTORY 11/12—Revision 0: Initial Version
Rev. 0 | Page 3 of 64 Document Outline Features Applications General Description Product Highlights Revision History Functional Block Diagram Specifications DC Specifications Digital Specifications DAC Latency Specifications Latency Variation Specifications0F AC Specifications Operating Speed Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Serial Port Operation Data Format Serial Port Pin Descriptions Serial Port Options Data Interface LVDS Input Data Ports Word Interface Mode Byte Interface Mode Data Interface Configuration Options LVDS Input Level Requirements Interface Delay Line Interface Timing Requirements SPI Sequence to Enable Delay Line-Based Mode FIFO Operation Resetting the FIFO Serial Port Initiated FIFO Reset Frame Initiated FIFO Reset Monitoring the FIFO Status Digital Datapath Interpolation Filters 2× Interpolation Mode 4× Interpolation Mode 8× Interpolation Mode Digital Modulation fS/4 Modulation NCO Modulation Updating the Frequency Tuning Word SPI Initiated Update Frame Initiated Update Datapath Configuration Digital Quadrature Gain and Phase Adjustment Quadrature Gain Adjustment Quadrature Phase Adjustment DC Offset Adjustment Inverse Sinc Filter Input Signal Power Detection and Protection Transmit Enable Function Digital Function Configuration Multidevice Synchronization and Fixed Latency Very Small Inherent Latency Variation Further Reducing the Latency Variation Set Up and Hold Timing Requirement Synchronization Implementation Synchronization Procedures Synchronization Procedure for PLL Off Synchronization Procedure for PLL On Interrupt Request Operation Interrupt Working Mechanism Interrupt Service Routine Temperature Sensor DAC Input Clock Configurations Driving the DACCLK and REFCLK Inputs Direct Clocking Clock Multiplication PLL Settings Configuring the VCO Tuning Band Automatic VCO Band Select Manual VCO Band Select Automatic Mode Sequence Manual Mode Analog Outputs Transmit DAC Operation Transmit DAC Transfer Function Transmit DAC Output Configurations Interfacing to Modulators Baseband Filter Implementation Reducing LO Leakage and Unwanted Sidebands Example Start-Up Routine Device Configuration and Start-Up Sequence Derived PLL Settings Derived NCO Settings Start-Up Sequence Device Configuration Register Map and Description SPI Configure Register Power-Down Control Register Interrupt Enable0 Register Interrupt Enable1 Register Interrupt Flag0 Register Interrupt Flag1 Register Interrupt Select0 Register Interrupt Select1 Register DAC Clock Receiver Control Register Ref Clock Receiver Control Register PLL Control Register PLL Control Register PLL Control Register PLL Status Register PLL Status Register IDAC FS Adjust LSB Register IDAC FS Adjust MSB Register QDAC FS Adjust LSB Register QDAC FS Adjust MSB Register Die Temperature Sensor Control Register Die Temperature LSB Register Die Temperature MSB Register Chip ID Register Interrupt Configuation Register Sync CTRL Register Frame Reset CTRL Register FIFO Level Configuration Register FIFO Level Readback Register FIFO CTRL Register Data Format Select Register Datapath Control Register Interpolation Control Register Over Threshold CTRL0 Register Over Threshold CTRL1 Register Over Threshold CTRL2 Register Input Power Readback LSB Register Input Power Readback MSB Register NCO Control Register NCO_FREQ_TUNING_WORD0 Register NCO_FREQ_TUNING_WORD1 Register NCO_FREQ_TUNING_WORD2 Register NCO_FREQ_TUNING_WORD3 Register NCO_PHASE_OFFSET0 Register NCO_PHASE_OFFSET1 Register IQ_PHASE_ADJ0 Register IQ_PHASE_ADJ1 Register IDAC_DC_OFFSET0 Register IDAC_DC_OFFSET1 Register QDAC_DC_OFFSET0 Register QDAC_DC_OFFSET1 Register IDAC_GAIN_ADJ Register QDAC_GAIN_ADJ Register Gain Step Control0 Register Gain Step Control1 Register TX Enable Control Register DAC Output Control Register Data Receiver Test Control Register Data Receiver Test Control Register Device Configuration0 Register Version Register Device Configuration1 Register Device Configuration2 Register DAC Latency and System Skews DAC Latency Variations FIFO Latency Variation Clock Generation Latency Variation Correcting System Skews Packaging and Ordering Information Outline Dimensions Ordering Guide
Data Sheet AD9142
PLL Status Register ... 48 NCO_PHASE_OFFSET1 Register .. 55 IDAC FS Adjust LSB Register .. 48 IQ_PHASE_ADJ0 Register .. 55 IDAC FS Adjust MSB Register .. 48 IQ_PHASE_ADJ1 Register .. 55 QDAC FS Adjust LSB Register .. 48 IDAC_DC_OFFSET0 Register .. 55 QDAC FS Adjust MSB Register .. 49 IDAC_DC_OFFSET1 Register .. 55 Die Temperature Sensor Control Register ... 49 QDAC_DC_OFFSET0 Register .. 55 Die Temperature LSB Register .. 49 QDAC_DC_OFFSET1 Register .. 56 Die Temperature MSB Register ... 49 IDAC_GAIN_ADJ Register... 56 Chip ID Register .. 49 QDAC_GAIN_ADJ Register ... 56 Interrupt Configuation Register ... 50 Gain Step Control0 Register .. 56 Sync CTRL Register .. 50 Gain Step Control1 Register .. 56 Frame Reset CTRL Register ... 50 TX Enable Control Register .. 57 FIFO Level Configuration Register .. 51 DAC Output Control Register .. 57 FIFO Level Readback Register .. 51 Data Receiver Test Control Register ... 57 FIFO CTRL Register ... 51 Data Receiver Test Control Register ... 57 Data Format Select Register ... 52 Device Configuration0 Register .. 58 Datapath Control Register ... 52 Version Register .. 58 Interpolation Control Register .. 52 Device Configuration1 Register .. 58 Over Threshold CTRL0 Register .. 53 Device Configuration2 Register .. 58 Over Threshold CTRL1 Register .. 53 DAC Latency and System Skews ... 59 Over Threshold CTRL2 Register .. 53 DAC Latency Variations... 59 Input Power Readback LSB Register .. 53 FIFO Latency Variation .. 59 Input Power Readback MSB Register ... 53 Clock Generation Latency Variation .. 60 NCO Control Register .. 54 Correcting System Skews ... 60 NCO_FREQ_TUNING_WORD0 Register ... 54 Packaging and Ordering Information .. 61 NCO_FREQ_TUNING_WORD1 Register ... 54 Outline Dimensions.. 61 NCO_FREQ_TUNING_WORD2 Register ... 54 Ordering Guide ... 61 NCO_FREQ_TUNING_WORD3 Register ... 54 NCO_PHASE_OFFSET0 Register .. 54
REVISION HISTORY 11/12—Revision 0: Initial Version
Rev. 0 | Page 3 of 64 Document Outline Features Applications General Description Product Highlights Revision History Functional Block Diagram Specifications DC Specifications Digital Specifications DAC Latency Specifications Latency Variation Specifications0F AC Specifications Operating Speed Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Serial Port Operation Data Format Serial Port Pin Descriptions Serial Port Options Data Interface LVDS Input Data Ports Word Interface Mode Byte Interface Mode Data Interface Configuration Options LVDS Input Level Requirements Interface Delay Line Interface Timing Requirements SPI Sequence to Enable Delay Line-Based Mode FIFO Operation Resetting the FIFO Serial Port Initiated FIFO Reset Frame Initiated FIFO Reset Monitoring the FIFO Status Digital Datapath Interpolation Filters 2× Interpolation Mode 4× Interpolation Mode 8× Interpolation Mode Digital Modulation fS/4 Modulation NCO Modulation Updating the Frequency Tuning Word SPI Initiated Update Frame Initiated Update Datapath Configuration Digital Quadrature Gain and Phase Adjustment Quadrature Gain Adjustment Quadrature Phase Adjustment DC Offset Adjustment Inverse Sinc Filter Input Signal Power Detection and Protection Transmit Enable Function Digital Function Configuration Multidevice Synchronization and Fixed Latency Very Small Inherent Latency Variation Further Reducing the Latency Variation Set Up and Hold Timing Requirement Synchronization Implementation Synchronization Procedures Synchronization Procedure for PLL Off Synchronization Procedure for PLL On Interrupt Request Operation Interrupt Working Mechanism Interrupt Service Routine Temperature Sensor DAC Input Clock Configurations Driving the DACCLK and REFCLK Inputs Direct Clocking Clock Multiplication PLL Settings Configuring the VCO Tuning Band Automatic VCO Band Select Manual VCO Band Select Automatic Mode Sequence Manual Mode Analog Outputs Transmit DAC Operation Transmit DAC Transfer Function Transmit DAC Output Configurations Interfacing to Modulators Baseband Filter Implementation Reducing LO Leakage and Unwanted Sidebands Example Start-Up Routine Device Configuration and Start-Up Sequence Derived PLL Settings Derived NCO Settings Start-Up Sequence Device Configuration Register Map and Description SPI Configure Register Power-Down Control Register Interrupt Enable0 Register Interrupt Enable1 Register Interrupt Flag0 Register Interrupt Flag1 Register Interrupt Select0 Register Interrupt Select1 Register DAC Clock Receiver Control Register Ref Clock Receiver Control Register PLL Control Register PLL Control Register PLL Control Register PLL Status Register PLL Status Register IDAC FS Adjust LSB Register IDAC FS Adjust MSB Register QDAC FS Adjust LSB Register QDAC FS Adjust MSB Register Die Temperature Sensor Control Register Die Temperature LSB Register Die Temperature MSB Register Chip ID Register Interrupt Configuation Register Sync CTRL Register Frame Reset CTRL Register FIFO Level Configuration Register FIFO Level Readback Register FIFO CTRL Register Data Format Select Register Datapath Control Register Interpolation Control Register Over Threshold CTRL0 Register Over Threshold CTRL1 Register Over Threshold CTRL2 Register Input Power Readback LSB Register Input Power Readback MSB Register NCO Control Register NCO_FREQ_TUNING_WORD0 Register NCO_FREQ_TUNING_WORD1 Register NCO_FREQ_TUNING_WORD2 Register NCO_FREQ_TUNING_WORD3 Register NCO_PHASE_OFFSET0 Register NCO_PHASE_OFFSET1 Register IQ_PHASE_ADJ0 Register IQ_PHASE_ADJ1 Register IDAC_DC_OFFSET0 Register IDAC_DC_OFFSET1 Register QDAC_DC_OFFSET0 Register QDAC_DC_OFFSET1 Register IDAC_GAIN_ADJ Register QDAC_GAIN_ADJ Register Gain Step Control0 Register Gain Step Control1 Register TX Enable Control Register DAC Output Control Register Data Receiver Test Control Register Data Receiver Test Control Register Device Configuration0 Register Version Register Device Configuration1 Register Device Configuration2 Register DAC Latency and System Skews DAC Latency Variations FIFO Latency Variation Clock Generation Latency Variation Correcting System Skews Packaging and Ordering Information Outline Dimensions Ordering Guide
