Datasheet AD5379 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 40-Channel, 14-Bit, Parallel and Serial Input, Bipolar Voltage-Output DAC |
| Pages / Page | 29 / 10 — AD5379. PARALLEL INTERFACE. Table 5. Parameter. Limit at TMIN to TMAX … |
| Revision | B |
| File Format / Size | PDF / 460 Kb |
| Document Language | English |
AD5379. PARALLEL INTERFACE. Table 5. Parameter. Limit at TMIN to TMAX Unit. Description
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AD5379 PARALLEL INTERFACE
VCC = 2.7 V to 5.5 V; VDD = 11.4 V to 16.5 V; VSS = −11.4 V to −16.5 V; AGND = DGND = DUTGND = 0 V; VREF(+) = 5 V; VREF(−) = −3.5 V, FIFOEN = 0 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 5. Parameter 1 , 2 , 3 Limit at TMIN to TMAX Unit Description
t0 4.5 ns min REG0, REG1, address to WR rising edge setup time. t1 4.5 ns min REG0, REG1, address to WR rising edge hold time. t2 10 ns min CS pulse width low. t3 10 ns min WR pulse width low. t4 0 ns min CS to WR falling edge setup time. t5 0 ns min WR to CS rising edge hold time. t6 4.5 ns min Data to WR rising edge setup time. t7 4.5 ns min Data to WR rising edge hold time. t8 20 ns min WR pulse width high. t9 240 ns min Minimum WR cycle time (single-channel write). t 4 10 0/30 ns min/max WR rising edge to BUSY falling edge. t 4 11 330 ns max BUSY pulse width low (single-channel update). See Table 10. t12 0 ns min BUSY rising edge to WR rising edge. t13 30 ns min WR rising edge to LDAC falling edge. t14 20 ns min LDAC pulse width low. t 4 15 150 ns typ BUSY rising edge to DAC output response time. t16 20 ns min LDAC rising edge to WR rising edge. t17 0 ns min BUSY rising edge to LDAC falling edge. t18 100 ns typ LDAC falling edge to DAC output response time. t19 20/30 μs typ/ max DAC output settling time. t20 10 ns min CLR pulse width low. t21 350 ns max CLR/RESET pulse activation time. t22 10 ns min RESET pulse width low. t23 120 μs max RESET time indicated by BUSY low. 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tr = tf = 2 ns (10% to 90% of VCC), and timed from a voltage level of 1.2 V. 3 See Figure 6. 4 Measured with load circuit shown in Figure 2. Rev. B | Page 9 of 28 Document Outline FEATURES APPLICATIONS TABLE OF CONTENTS GENERAL DESCRIPTION SPECIFICATIONS AC CHARACTERISTICS TIMING CHARACTERISTICS SERIAL INTERFACE PARALLEL INTERFACE ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS FUNCTIONAL DESCRIPTION DAC ARCHITECTURE—GENERAL CHANNEL GROUPS TRANSFER FUNCTION VBIAS FUNCTION REFERENCE SELECTION Reference Selection Example CALIBRATION Calibration Example CLEAR FUNCTION Hardware Clear Software Clear /BUSY AND /LDAC FUNCTIONS FIFO VS. NON-FIFO OPERATION /BUSY INPUT FUNCTION POWER-ON RESET FUNCTION /RESET INPUT FUNCTION INCREMENT/DECREMENT FUNCTION INTERFACES PARALLEL INTERFACE / CS Pin /WR Pin REG1, REG0 Pins DB13 to DB0 Pins A7 to A0 Pins SERIAL INTERFACE /SYNC , DIN, SCLK DCEN SDO Standalone Mode Daisy-Chain Mode DATA DECODING ADDRESS DECODING POWER SUPPLY DECOUPLING POWER-ON TYPICAL APPLICATION CIRCUIT OUTLINE DIMENSIONS ORDERING GUIDE
AD5379 PARALLEL INTERFACE
VCC = 2.7 V to 5.5 V; VDD = 11.4 V to 16.5 V; VSS = −11.4 V to −16.5 V; AGND = DGND = DUTGND = 0 V; VREF(+) = 5 V; VREF(−) = −3.5 V, FIFOEN = 0 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 5. Parameter 1 , 2 , 3 Limit at TMIN to TMAX Unit Description
t0 4.5 ns min REG0, REG1, address to WR rising edge setup time. t1 4.5 ns min REG0, REG1, address to WR rising edge hold time. t2 10 ns min CS pulse width low. t3 10 ns min WR pulse width low. t4 0 ns min CS to WR falling edge setup time. t5 0 ns min WR to CS rising edge hold time. t6 4.5 ns min Data to WR rising edge setup time. t7 4.5 ns min Data to WR rising edge hold time. t8 20 ns min WR pulse width high. t9 240 ns min Minimum WR cycle time (single-channel write). t 4 10 0/30 ns min/max WR rising edge to BUSY falling edge. t 4 11 330 ns max BUSY pulse width low (single-channel update). See Table 10. t12 0 ns min BUSY rising edge to WR rising edge. t13 30 ns min WR rising edge to LDAC falling edge. t14 20 ns min LDAC pulse width low. t 4 15 150 ns typ BUSY rising edge to DAC output response time. t16 20 ns min LDAC rising edge to WR rising edge. t17 0 ns min BUSY rising edge to LDAC falling edge. t18 100 ns typ LDAC falling edge to DAC output response time. t19 20/30 μs typ/ max DAC output settling time. t20 10 ns min CLR pulse width low. t21 350 ns max CLR/RESET pulse activation time. t22 10 ns min RESET pulse width low. t23 120 μs max RESET time indicated by BUSY low. 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tr = tf = 2 ns (10% to 90% of VCC), and timed from a voltage level of 1.2 V. 3 See Figure 6. 4 Measured with load circuit shown in Figure 2. Rev. B | Page 9 of 28 Document Outline FEATURES APPLICATIONS TABLE OF CONTENTS GENERAL DESCRIPTION SPECIFICATIONS AC CHARACTERISTICS TIMING CHARACTERISTICS SERIAL INTERFACE PARALLEL INTERFACE ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS FUNCTIONAL DESCRIPTION DAC ARCHITECTURE—GENERAL CHANNEL GROUPS TRANSFER FUNCTION VBIAS FUNCTION REFERENCE SELECTION Reference Selection Example CALIBRATION Calibration Example CLEAR FUNCTION Hardware Clear Software Clear /BUSY AND /LDAC FUNCTIONS FIFO VS. NON-FIFO OPERATION /BUSY INPUT FUNCTION POWER-ON RESET FUNCTION /RESET INPUT FUNCTION INCREMENT/DECREMENT FUNCTION INTERFACES PARALLEL INTERFACE / CS Pin /WR Pin REG1, REG0 Pins DB13 to DB0 Pins A7 to A0 Pins SERIAL INTERFACE /SYNC , DIN, SCLK DCEN SDO Standalone Mode Daisy-Chain Mode DATA DECODING ADDRESS DECODING POWER SUPPLY DECOUPLING POWER-ON TYPICAL APPLICATION CIRCUIT OUTLINE DIMENSIONS ORDERING GUIDE
