Datasheet AD210 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Precision, Wide Bandwidth 3-Port Isolation Amplifier |
| Pages / Page | 9 / 5 — AD210. CHANNEL OUTPUTS. 0.1". GRID. POWER. GAIN. 47.5k. VOUT. CHANNEL … |
| Revision | A |
| File Format / Size | PDF / 340 Kb |
| Document Language | English |
AD210. CHANNEL OUTPUTS. 0.1". GRID. POWER. GAIN. 47.5k. VOUT. CHANNEL INPUTS. 200. VSIG. Synchronization:. 50k. ISS. +VOSS. 100k. –VISS. OSS. OFFSET
Model Line for this Datasheet
Text Version of Document
AD210
low side of the signal source. This will not work if the source has
CHANNEL OUTPUTS
another current path to input common or if current flows in the
1 2 3
signal source LO lead. To minimize CMR degradation, keep the resistor in series with the input LO below a few hundred ohms. Figure 5 also shows the preferred gain adjustment circuit. The circuit shows RF of 50 kΩ, and will work for gains of ten or greater. The adjustment becomes less effective at lower gains (its effect is halved at G = 2) so that the pot will have to be a larger fraction of the total R
0.1"
F at low gain. At G = 1 (follower)
GRID
the gain cannot be adjusted downward without compromising input impedance; it is better to adjust gain at the signal source
POWER
or after the output. Figure 6 shows the input adjustment circuit for use when the input amplifier is configured in the inverting mode. The offset adjustment nulls the voltage at the summing node. This is pref- erable to current injection because it is less affected by subse- quent gain adjustment. Gain adjustment is made in the feedback and will work for gains from 1 V/V to 100 V/V.
GAIN 47.5k
Ω
R R R R R R 16 G F G F G F 5k
Ω
VOUT 1 2 3 17 1 CHANNEL INPUTS RS 19
Figure 8. PCB Layout for Multichannel Applications with
200
Ω
AD210 VSIG
Gain
18 2 Synchronization:
The AD210 is insensitive to the clock of an
50k
Ω
+V 14 ISS
adjacent unit, eliminating the need to synchronize the clocks.
+VOSS 3 100k
Ω However, in rare instances channel to channel pick-up may
15 –VISS –V 4 OSS
occur if input signal wires are bundled together. If this happens,
OFFSET 30 29
shielded input cables are recommended.
+15V PERFORMANCE CHARACTERISTICS
Figure 6. Adjustments for Inverting Input
Common-Mode Rejection:
Figure 9 shows the common- Figure 7 shows how offset adjustments can be made at the out- mode rejection of the AD210 versus frequency, gain and input put, by offsetting the floating output port. In this circuit, ± 15 V source resistance. For maximum common-mode rejection of would be supplied by a separate source. The AD210’s output unwanted signals, keep the input source resistance low and care- amplifier is fixed at unity, therefore, output gain must be made fully lay out the input, avoiding excessive stray capacitance at in a subsequent stage. the input terminals.
180 16 G = 100 160 R 17 1 LO = 0 G = 1 V
Ω
OUT 19 140 AD210 50k
Ω
RLO = 500 18 2
Ω
120 R 200
Ω
LO = 0
Ω
0.1µF +V 14 ISS +VOSS 3 100 CMR – dB RLO = 10k 100k
Ω
15 –VISS –V 4 OSS OFFSET 80 RLO 30 = 10k 29 +15V –15V
Ω
60 +15V
Figure 7. Output-Side Offset Adjustment
40 10 20 50 60 100 200 500 1k 2k 5k 10k PCB Layout for Multichannel Applications:
The unique
FREQUENCY – Hz
pinout positioning minimizes board space constraints for multi- Figure 9. Common-Mode Rejection vs. Frequency channel applications. Figure 8 shows the recommended printed circuit board layout for a noninverting input configuration with gain. –4– REV. A
low side of the signal source. This will not work if the source has
CHANNEL OUTPUTS
another current path to input common or if current flows in the
1 2 3
signal source LO lead. To minimize CMR degradation, keep the resistor in series with the input LO below a few hundred ohms. Figure 5 also shows the preferred gain adjustment circuit. The circuit shows RF of 50 kΩ, and will work for gains of ten or greater. The adjustment becomes less effective at lower gains (its effect is halved at G = 2) so that the pot will have to be a larger fraction of the total R
0.1"
F at low gain. At G = 1 (follower)
GRID
the gain cannot be adjusted downward without compromising input impedance; it is better to adjust gain at the signal source
POWER
or after the output. Figure 6 shows the input adjustment circuit for use when the input amplifier is configured in the inverting mode. The offset adjustment nulls the voltage at the summing node. This is pref- erable to current injection because it is less affected by subse- quent gain adjustment. Gain adjustment is made in the feedback and will work for gains from 1 V/V to 100 V/V.
GAIN 47.5k
Ω
R R R R R R 16 G F G F G F 5k
Ω
VOUT 1 2 3 17 1 CHANNEL INPUTS RS 19
Figure 8. PCB Layout for Multichannel Applications with
200
Ω
AD210 VSIG
Gain
18 2 Synchronization:
The AD210 is insensitive to the clock of an
50k
Ω
+V 14 ISS
adjacent unit, eliminating the need to synchronize the clocks.
+VOSS 3 100k
Ω However, in rare instances channel to channel pick-up may
15 –VISS –V 4 OSS
occur if input signal wires are bundled together. If this happens,
OFFSET 30 29
shielded input cables are recommended.
+15V PERFORMANCE CHARACTERISTICS
Figure 6. Adjustments for Inverting Input
Common-Mode Rejection:
Figure 9 shows the common- Figure 7 shows how offset adjustments can be made at the out- mode rejection of the AD210 versus frequency, gain and input put, by offsetting the floating output port. In this circuit, ± 15 V source resistance. For maximum common-mode rejection of would be supplied by a separate source. The AD210’s output unwanted signals, keep the input source resistance low and care- amplifier is fixed at unity, therefore, output gain must be made fully lay out the input, avoiding excessive stray capacitance at in a subsequent stage. the input terminals.
180 16 G = 100 160 R 17 1 LO = 0 G = 1 V
Ω
OUT 19 140 AD210 50k
Ω
RLO = 500 18 2
Ω
120 R 200
Ω
LO = 0
Ω
0.1µF +V 14 ISS +VOSS 3 100 CMR – dB RLO = 10k 100k
Ω
15 –VISS –V 4 OSS OFFSET 80 RLO 30 = 10k 29 +15V –15V
Ω
60 +15V
Figure 7. Output-Side Offset Adjustment
40 10 20 50 60 100 200 500 1k 2k 5k 10k PCB Layout for Multichannel Applications:
The unique
FREQUENCY – Hz
pinout positioning minimizes board space constraints for multi- Figure 9. Common-Mode Rejection vs. Frequency channel applications. Figure 8 shows the recommended printed circuit board layout for a noninverting input configuration with gain. –4– REV. A
