Datasheet LTC3838-1 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Dual, Fast, Accurate Step-Down DC/DC Controller with Dual Differential Output Sensing |
| Pages / Page | 54 / 10 — pin FuncTions. DFB2 (Pin 1):. PHASMD (Pin 9):. ITH1, ITH2 (Pin 10, Pin … |
| File Format / Size | PDF / 890 Kb |
| Document Language | English |
pin FuncTions. DFB2 (Pin 1):. PHASMD (Pin 9):. ITH1, ITH2 (Pin 10, Pin 3):. VRNG (Pin 2):. TRACK/SS1, TRACK/SS2 (Pin 11, Pin 4):
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Text Version of Document
LTC3838-1
pin FuncTions V + DFB2 (Pin 1):
Differential Feedback Amplifier (+) Input
PHASMD (Pin 9):
Phase Selector Input. This pin determines of Channel 2. As shown in the Functional Diagram, con- the relative phases of channels and the CLKOUT signal. nect this pin to a 3-resistor feedback divider network, With zero phase being defined as the rising edge of TG1: which is composed of RDFB1 and RDFB2 from this pin to Pulling this pin to SGND locks TG2 to 180°, and CLKOUT the negative and positive terminals of VOUT2 respectively, to 60°. Connecting this pin to INTVCC locks TG2 to 240° and a third resistor from this pin to local SGND. The and CLKOUT to 120°. Floating this pin locks TG2 to 180° third resistor must have a value equal to RDFB1//RDFB2 and CLKOUT to 90°. for accurate differential regulation. With the 3-resistor
ITH1, ITH2 (Pin 10, Pin 3):
Current Control Threshold. This feedback divider network, the LTC3838-1 will regulate the pin is the output of the error amplifier and the switching differential output VOUT2 to 0.6V • (RDFB1 + RDFB2)/RDFB1. regulator’s compensation point. The current comparator
VRNG (Pin 2):
Current Sense Voltage Range Input. The maxi- threshold increases with this control voltage. The voltage mum sense voltage between SENSE1,2+ and SENSE1,2– of ranges from 0V to 2.4V, with 0.8V corresponding to zero either channel, VSENSE(MAX)1,2, is 30mV if VRNG is tied to sense voltage (zero inductor valley current). SGND, and 60mV if VRNG is tied to INTVCC.
TRACK/SS1, TRACK/SS2 (Pin 11, Pin 4):
External Tracking
MODE/PLLIN (Pin 5):
Operation Mode Selection or Exter- and Soft-Start Input. The LTC3838-1 regulates differen- nal Clock Synchronization Input. When this pin is tied to tial feedback voltages (V + – OUTSENSE1 – VOUTSENSE1 ) and INTV + – CC, forced continuous mode operation is selected. Ty- (2 • VDFB2 – VDFB2 ) to the smaller of 0.6V or the volt- ing this pin to SGND al ows discontinuous mode operation. age on the TRACK/SS1,2 pins respectively. An internal When an external clock is applied at this pin, both channels 1µA temperature-independent pull-up current source is operate in forced continuous mode and synchronize to the connected to each TRACK/SS pin. A capacitor to ground external clock. This pin has an internal 600k pull-down at this pin sets the ramp time to the final regulated output resistor to SGND. voltage. Alternatively, another voltage supply connected
CLKOUT (Pin 6):
Clock Output of Internal Clock Genera- to this pin allows the output to track the other supply tor. Its output level swings between INTV during start-up. CC and SGND. If clock input is present at the MODE/PLLIN pin, it will
V + OUTSENSE1 (Pin 12):
Differential Output Sense Amplifier be synchronized to the input clock, with phase set by the (+) Input of Channel 1. Connect this pin to a feedback PHASMD pin. If no clock is present at MODE/PLLIN, its resistor divider between the positive and negative output frequency will be set by the RT pin. To synchronize other capacitor terminals of VOUT1 as shown in the Functional controllers, it can be connected to their MODE/PLLIN pins. Diagram. In normal operation, the LTC3838-1 will at-
SGND (Pin 7):
Signal Ground. All small-signal analog and tempt to regulate the differential output voltage VOUT1 compensation components should be connected to this to 0.6V divided by the feedback resistor divider ratio, i.e, ground. Connect SGND to the exposed pad and PGND pin 0.6V • (RFB1 + RFB2)/RFB1. using a single PCB trace. Shorting the V + OUTSENSE1 pin to INTVCC will disable
RT (Pin 8):
Clock Generator Frequency Programming Pin. channel 1’s error amplifier, and internally connect ITH1 Connect an external resistor from RT to SGND to program to ITH2. (As a result, TRACK/SS1 is no longer functional the switching frequency between 200kHz and 2MHz. An and PGOOD1 is always pulling low.) By doing so, this external clock applied to MODE/PLLIN should be within part can function as a dual phase, single VOUT step-down ±30% of this programmed frequency to ensure frequency controller, and the two channels use a single channel 2 lock. When the RT pin is floating, the frequency is internally error amplifier for the ITH output and compensation. set to be slightly under 200kHz. 38381fa 10 For more information www.linear.com/3838-1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Electrical Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
pin FuncTions V + DFB2 (Pin 1):
Differential Feedback Amplifier (+) Input
PHASMD (Pin 9):
Phase Selector Input. This pin determines of Channel 2. As shown in the Functional Diagram, con- the relative phases of channels and the CLKOUT signal. nect this pin to a 3-resistor feedback divider network, With zero phase being defined as the rising edge of TG1: which is composed of RDFB1 and RDFB2 from this pin to Pulling this pin to SGND locks TG2 to 180°, and CLKOUT the negative and positive terminals of VOUT2 respectively, to 60°. Connecting this pin to INTVCC locks TG2 to 240° and a third resistor from this pin to local SGND. The and CLKOUT to 120°. Floating this pin locks TG2 to 180° third resistor must have a value equal to RDFB1//RDFB2 and CLKOUT to 90°. for accurate differential regulation. With the 3-resistor
ITH1, ITH2 (Pin 10, Pin 3):
Current Control Threshold. This feedback divider network, the LTC3838-1 will regulate the pin is the output of the error amplifier and the switching differential output VOUT2 to 0.6V • (RDFB1 + RDFB2)/RDFB1. regulator’s compensation point. The current comparator
VRNG (Pin 2):
Current Sense Voltage Range Input. The maxi- threshold increases with this control voltage. The voltage mum sense voltage between SENSE1,2+ and SENSE1,2– of ranges from 0V to 2.4V, with 0.8V corresponding to zero either channel, VSENSE(MAX)1,2, is 30mV if VRNG is tied to sense voltage (zero inductor valley current). SGND, and 60mV if VRNG is tied to INTVCC.
TRACK/SS1, TRACK/SS2 (Pin 11, Pin 4):
External Tracking
MODE/PLLIN (Pin 5):
Operation Mode Selection or Exter- and Soft-Start Input. The LTC3838-1 regulates differen- nal Clock Synchronization Input. When this pin is tied to tial feedback voltages (V + – OUTSENSE1 – VOUTSENSE1 ) and INTV + – CC, forced continuous mode operation is selected. Ty- (2 • VDFB2 – VDFB2 ) to the smaller of 0.6V or the volt- ing this pin to SGND al ows discontinuous mode operation. age on the TRACK/SS1,2 pins respectively. An internal When an external clock is applied at this pin, both channels 1µA temperature-independent pull-up current source is operate in forced continuous mode and synchronize to the connected to each TRACK/SS pin. A capacitor to ground external clock. This pin has an internal 600k pull-down at this pin sets the ramp time to the final regulated output resistor to SGND. voltage. Alternatively, another voltage supply connected
CLKOUT (Pin 6):
Clock Output of Internal Clock Genera- to this pin allows the output to track the other supply tor. Its output level swings between INTV during start-up. CC and SGND. If clock input is present at the MODE/PLLIN pin, it will
V + OUTSENSE1 (Pin 12):
Differential Output Sense Amplifier be synchronized to the input clock, with phase set by the (+) Input of Channel 1. Connect this pin to a feedback PHASMD pin. If no clock is present at MODE/PLLIN, its resistor divider between the positive and negative output frequency will be set by the RT pin. To synchronize other capacitor terminals of VOUT1 as shown in the Functional controllers, it can be connected to their MODE/PLLIN pins. Diagram. In normal operation, the LTC3838-1 will at-
SGND (Pin 7):
Signal Ground. All small-signal analog and tempt to regulate the differential output voltage VOUT1 compensation components should be connected to this to 0.6V divided by the feedback resistor divider ratio, i.e, ground. Connect SGND to the exposed pad and PGND pin 0.6V • (RFB1 + RFB2)/RFB1. using a single PCB trace. Shorting the V + OUTSENSE1 pin to INTVCC will disable
RT (Pin 8):
Clock Generator Frequency Programming Pin. channel 1’s error amplifier, and internally connect ITH1 Connect an external resistor from RT to SGND to program to ITH2. (As a result, TRACK/SS1 is no longer functional the switching frequency between 200kHz and 2MHz. An and PGOOD1 is always pulling low.) By doing so, this external clock applied to MODE/PLLIN should be within part can function as a dual phase, single VOUT step-down ±30% of this programmed frequency to ensure frequency controller, and the two channels use a single channel 2 lock. When the RT pin is floating, the frequency is internally error amplifier for the ITH output and compensation. set to be slightly under 200kHz. 38381fa 10 For more information www.linear.com/3838-1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Electrical Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
