Datasheet AD7691-EP (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 18-Bit, 1.5 LSB INL, 250 kSPS PulSAR® Differential ADC in MSOP/QFN |
| Pages / Page | 13 / 6 — AD7691-EP. Enhanced Product. Table 4. Parameter. Symbol Min Typ Max Unit. … |
| Revision | A |
| File Format / Size | PDF / 444 Kb |
| Document Language | English |
AD7691-EP. Enhanced Product. Table 4. Parameter. Symbol Min Typ Max Unit. Timing Diagrams. 500µA. IOL. TO SDO. 1.4V. 50pF. 70% VIO. 30% VIO
Model Line for this Datasheet
Text Version of Document
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AD7691-EP Enhanced Product
VDD = 2.3 V to 4.5 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted. See Figure 3 and Figure 4 for load conditions.
Table 4. Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available tCONV 0.5 3.7 μs Acquisition Time tACQ 1.8 μs Time Between Conversions tCYC 5.5 μs CNV Pulse Width (CS Mode) tCNVH 10 ns SCK Period (CS Mode) tSCK 25 ns SCK Period (Chain Mode) tSCK VIO Above 3 V 29 ns VIO Above 2.7 V 35 ns VIO Above 2.3 V 40 ns SCK Low Time tSCKL 12 ns SCK High Time tSCKH 12 ns SCK Falling Edge to Data Remains Valid tHSDO 5 ns SCK Falling Edge to Data Valid Delay tDSDO VIO Above 3 V 24 ns VIO Above 2.7 V 30 ns VIO Above 2.3 V 35 ns CNV or SDI Low to SDO D17 MSB Valid (CS Mode) tEN VIO Above 2.7 V 18 ns VIO Above 2.3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 25 ns SDI Valid Setup Time from CNV Rising Edge (CS Mode) tSSDICNV 30 ns SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 8 ns SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 8 ns SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 10 ns SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI 36
Timing Diagrams 500µA IOL TO SDO 1.4V CL 50pF
02 0
500µA I
6-
OH
215 1 Figure 3. Load Circuit for Digital Interface Timing
70% VIO 30% VIO tDELAY tDELAY 2V OR VIO – 0.5V1 2V OR VIO – 0.5V1 0.8V OR 0.5V2 0.8V OR 0.5V2
003
12V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V. 20.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
12156- Figure 4. Voltage Levels for Timing Rev. A | Page 6 of 13 Document Outline Features Enhanced Product Features Applications Application Diagram General Description Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Outline Dimensions Ordering Guide
AD7691-EP Enhanced Product
VDD = 2.3 V to 4.5 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted. See Figure 3 and Figure 4 for load conditions.
Table 4. Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available tCONV 0.5 3.7 μs Acquisition Time tACQ 1.8 μs Time Between Conversions tCYC 5.5 μs CNV Pulse Width (CS Mode) tCNVH 10 ns SCK Period (CS Mode) tSCK 25 ns SCK Period (Chain Mode) tSCK VIO Above 3 V 29 ns VIO Above 2.7 V 35 ns VIO Above 2.3 V 40 ns SCK Low Time tSCKL 12 ns SCK High Time tSCKH 12 ns SCK Falling Edge to Data Remains Valid tHSDO 5 ns SCK Falling Edge to Data Valid Delay tDSDO VIO Above 3 V 24 ns VIO Above 2.7 V 30 ns VIO Above 2.3 V 35 ns CNV or SDI Low to SDO D17 MSB Valid (CS Mode) tEN VIO Above 2.7 V 18 ns VIO Above 2.3 V 22 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 25 ns SDI Valid Setup Time from CNV Rising Edge (CS Mode) tSSDICNV 30 ns SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 8 ns SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 8 ns SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 10 ns SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI 36
Timing Diagrams 500µA IOL TO SDO 1.4V CL 50pF
02 0
500µA I
6-
OH
215 1 Figure 3. Load Circuit for Digital Interface Timing
70% VIO 30% VIO tDELAY tDELAY 2V OR VIO – 0.5V1 2V OR VIO – 0.5V1 0.8V OR 0.5V2 0.8V OR 0.5V2
003
12V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V. 20.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
12156- Figure 4. Voltage Levels for Timing Rev. A | Page 6 of 13 Document Outline Features Enhanced Product Features Applications Application Diagram General Description Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Outline Dimensions Ordering Guide
