Datasheet AD7466-KGD (Analog Devices)

1.6 V, Micropower 12-Bit ADC Known Good Die AD7466-KGD FEATURES FUNCTIONAL BLOCK DIAGRAM Specified for V VDD DD of 1.6 V to 3.6 V Low power 0.62 mW typical at 100 kSPS with 3 V supplies 12-BIT 0.48 mW typical at 50 kSPS with 3.6 V supplies SUCCESSIVE VIN T/H APPROXIMATION 0.12 mW typical at 100 kSPS with 1.6 V supplies ADC Fast throughput rate: 200 kSPS Wide input bandwidth: 71 dB SNR at 30 kHz input frequency Flexible power/serial clock speed management SCLK No pipeline delays CONTROL SDATA LOGIC High speed serial interface CS SPI/QSPI™/MICROWIRE™/DSP compatible AD7466-KGD Automatic power-down
001
Power-down mode: 8 nA typical GND
10315-

Figure 1.
APPLICATIONS Battery-powered systems Medical instruments Remote data acquisition Isolated data acquisition GENERAL DESCRIPTION PRODUCT HIGHLIGHTS
The AD7466-KGD1 are 12-bit, high speed, low power, 1. Specified for supply voltages of 1.6 V to 3.6 V. successive approximation analog-to-digital converter (ADC). 2. High throughput rate with low power consumption. The part operates from a single 1.6 V to 3.6 V power supply and Power consumption in normal mode of operation at features throughput rates up to 200 kSPS with low power 100 kSPS and 3 V is 0.9 mW maximum. dissipation. The part contains a low noise, wide bandwidth 3. Flexible power/serial clock speed management. track-and-hold amplifier, which can handle input frequencies in The conversion rate is determined by the serial clock, excess of 3 MHz. al owing the conversion time to be reduced through The conversion process and data acquisition are controlled increases in the serial clock speed. Automatic power-down using CS and the serial clock, al owing the device to interface after conversion al ows the average power consumption to with microprocessors or DSPs. The input signal is sampled on be reduced when in power-down. Current consumption is the fal ing edge of CS, and the conversion is also initiated at this 0.1 µA maximum and 8 nA typically when in power-down. point. There are no pipeline delays associated with the part. 4. Reference derived from the power supply. 5. No pipeline delay. The reference for the part is taken internal y from VDD. This 6. The part features a standard successive approximation al ows the widest dynamic input range to the ADC. Thus, the ADC with accurate control of conversions via a CS input. analog input range for the part is 0 V to VDD. The conversion rate is determined by the SCLK. 1 Protected by U.S. Patent No. 6,681,332.
Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2011–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING EXAMPLES Timing Example 1 Timing Example 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS DIE SPECIFICATIONS AND ASSEMBLY RECOMMENDATIONS ORDERING GUIDE