Datasheet ADA4350 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | FET Input Analog Front End with ADC Driver |
| Pages / Page | 37 / 3 — Data Sheet. ADA4350. SPECIFICATIONS ±5 V FULL SYSTEM. Table 1. Parameter. … |
| Revision | B |
| File Format / Size | PDF / 814 Kb |
| Document Language | English |
Data Sheet. ADA4350. SPECIFICATIONS ±5 V FULL SYSTEM. Table 1. Parameter. Test Conditions/Comments. Min. Typ. Max. Unit
Model Line for this Datasheet
Text Version of Document
link to page 1
Data Sheet ADA4350 SPECIFICATIONS ±5 V FULL SYSTEM
TA = 25°C, +VS = +5 V, −VS = −5 V, RL = 1 kΩ differential, unless otherwise specified.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE −3 dB Bandwidth Gain (G) = −5, VOUT = 200 mV p-p 20 MHz G = −5, VOUT = 2 V p-p 12 MHz Slew Rate VOUT = 2 V step, 10% to 90% 60 V/µs HARMONIC PERFORMANCE Harmonic Distortion (HD2/HD3) G = −5, fC = 100 kHz −95/−104 dBc G = −5, fC = 1 MHz −77/−78 dBc DC PERFORMANCE Input Bias Current At 25°C ±0.25 ±1 pA At 85°C ±8 ±25 pA INPUT CHARACTERISTICS Input Resistance Common mode 100 GΩ Input Capacitance Common mode 2 pF Differential mode 3 pF Input Common-Mode Voltage Range Common-mode rejection ratio (CMRR) > 80 dB −4.5 +3.8 V CMRR > 68 dB −5 +3.9 V Common-Mode Rejection VCM = ±3.0 V 92 104 dB OUTPUT CHARACTERISTICS Linear Output Current VOUT = 4 V p-p, 60 dB spurious-free dynamic 18 mA rms range (SFDR) Short-Circuit Current Sinking/sourcing 43/76 mA Settling Time to 0.1% G = −5, VOUT = 2 V step 100 ns ANALOG POWER SUPPLY (+VS, −VS) Operating Range 3.3 12 V Quiescent Current Enabled 8.5 10 mA M1 disabled (see Figure 1) 7 mA All disabled 2 µA Positive Power Supply Rejection Ratio 90 dB Negative Power Supply Rejection Ratio 85 dB DIGITAL SUPPLIES DVDD, DGND Digital Supply Range 3.3 5.5 V Quiescent Current Enabled 50 µA Disabled 0.6 µA +VS to DGND Head Room ≥3.3 V Rev. B | Page 3 of 37 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS ±5 V FULL SYSTEM ±5 V FET INPUT AMPLIFIER ±5 V INTERNAL SWITCHING NETWORK AND DIGITAL PINS ±5 V ADC DRIVER 5 V FULL SYSTEM 5 V FET INPUT AMPLIFIER 5 V INTERNAL SWITCHING NETWORK AND DIGITAL PINS 5 V ADC DRIVER TIMING SPECIFICATIONS Timing Diagrams for Serial Mode ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISITICS FULL SYSTEM FET INPUT AMPLIFIER ADC DRIVER TEST CIRCUITS THEORY OF OPERATION KELVIN SWITCHING TECHNIQUES APPLICATIONS INFORMATION CONFIGURING THE ADA4350 SELECTING THE TRANSIMPEDANCE GAIN PATHS MANUALLY OR THROUGH THE PARALLEL INTERFACE SELECTING THE TRANSIMPEDANCE GAIN PATHS THROUGH THE SPI INTERFACE (SERIAL MODE) SPICE MODEL TRANSIMPEDANCE AMPLIFIER DESIGN THEORY TRANSIMPEDANCE GAIN AMPLIFIER PERFORMANCE THE EFFECT OF LOW FEEDBACK RESISTOR RFx USING THE T NETWORK TO IMPLEMENT LARGE FEEDBACK RESISTOR VALUES OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet ADA4350 SPECIFICATIONS ±5 V FULL SYSTEM
TA = 25°C, +VS = +5 V, −VS = −5 V, RL = 1 kΩ differential, unless otherwise specified.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE −3 dB Bandwidth Gain (G) = −5, VOUT = 200 mV p-p 20 MHz G = −5, VOUT = 2 V p-p 12 MHz Slew Rate VOUT = 2 V step, 10% to 90% 60 V/µs HARMONIC PERFORMANCE Harmonic Distortion (HD2/HD3) G = −5, fC = 100 kHz −95/−104 dBc G = −5, fC = 1 MHz −77/−78 dBc DC PERFORMANCE Input Bias Current At 25°C ±0.25 ±1 pA At 85°C ±8 ±25 pA INPUT CHARACTERISTICS Input Resistance Common mode 100 GΩ Input Capacitance Common mode 2 pF Differential mode 3 pF Input Common-Mode Voltage Range Common-mode rejection ratio (CMRR) > 80 dB −4.5 +3.8 V CMRR > 68 dB −5 +3.9 V Common-Mode Rejection VCM = ±3.0 V 92 104 dB OUTPUT CHARACTERISTICS Linear Output Current VOUT = 4 V p-p, 60 dB spurious-free dynamic 18 mA rms range (SFDR) Short-Circuit Current Sinking/sourcing 43/76 mA Settling Time to 0.1% G = −5, VOUT = 2 V step 100 ns ANALOG POWER SUPPLY (+VS, −VS) Operating Range 3.3 12 V Quiescent Current Enabled 8.5 10 mA M1 disabled (see Figure 1) 7 mA All disabled 2 µA Positive Power Supply Rejection Ratio 90 dB Negative Power Supply Rejection Ratio 85 dB DIGITAL SUPPLIES DVDD, DGND Digital Supply Range 3.3 5.5 V Quiescent Current Enabled 50 µA Disabled 0.6 µA +VS to DGND Head Room ≥3.3 V Rev. B | Page 3 of 37 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS ±5 V FULL SYSTEM ±5 V FET INPUT AMPLIFIER ±5 V INTERNAL SWITCHING NETWORK AND DIGITAL PINS ±5 V ADC DRIVER 5 V FULL SYSTEM 5 V FET INPUT AMPLIFIER 5 V INTERNAL SWITCHING NETWORK AND DIGITAL PINS 5 V ADC DRIVER TIMING SPECIFICATIONS Timing Diagrams for Serial Mode ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISITICS FULL SYSTEM FET INPUT AMPLIFIER ADC DRIVER TEST CIRCUITS THEORY OF OPERATION KELVIN SWITCHING TECHNIQUES APPLICATIONS INFORMATION CONFIGURING THE ADA4350 SELECTING THE TRANSIMPEDANCE GAIN PATHS MANUALLY OR THROUGH THE PARALLEL INTERFACE SELECTING THE TRANSIMPEDANCE GAIN PATHS THROUGH THE SPI INTERFACE (SERIAL MODE) SPICE MODEL TRANSIMPEDANCE AMPLIFIER DESIGN THEORY TRANSIMPEDANCE GAIN AMPLIFIER PERFORMANCE THE EFFECT OF LOW FEEDBACK RESISTOR RFx USING THE T NETWORK TO IMPLEMENT LARGE FEEDBACK RESISTOR VALUES OUTLINE DIMENSIONS ORDERING GUIDE
