Datasheet Texas Instruments TMS320C6671ACYP25

Manufacturer	Texas Instruments
Series	TMS320C6671
Part Number	TMS320C6671ACYP25

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Eco Plan

Design Kits & Evaluation Modules

• Development Kits: TMDSEVM6678
  TMS320C6678 Evaluation Modules
  Lifecycle Status: Active (Recommended for new designs)
  
• Daughter Cards: TMDXEVMPCI
  AMC to PCIe Adapter Card
  Lifecycle Status: Active (Recommended for new designs)
  
• Development Kits: HL5CABLE
  Hyperlink Cable
  Lifecycle Status: Active (Recommended for new designs)
  
• JTAG Emulators/ Analyzers: TMDSEMU200-U
  XDS200 USB Debug Probe
  Lifecycle Status: Active (Recommended for new designs)
  
• JTAG Emulators/ Analyzers: TMDSEMU560V2STM-UE
  XDS560v2 System Trace USB & Ethernet Debug Probe
  Lifecycle Status: Active (Recommended for new designs)
  
• JTAG Emulators/ Analyzers: TMDSEMU560V2STM-U
  XDS560v2 System Trace USB Debug Probe
  Lifecycle Status: Active (Recommended for new designs)
  

Application Notes

• Download
  TI Keystone DSP Hyperlink SerDes IBIS-AMI Models
  PDF, 3.2 Mb, File published: Oct 9, 2014
  This document describes the organization, structure, and proper usage of the TI serializer and deserializer (SerDes) IBIS-AMI models for Keystone DSP Hyperlink interface.
• Download
  TI Keystone DSP PCIe SerDes IBIS-AMI Models
  PDF, 4.8 Mb, File published: Oct 9, 2014
  This document describes the organization, structure, and proper usage of the TI serializer and deserializer (SerDes) IBIS-AMI models for Keystone DSP PCIe interface.
• Download
  SerDes Implementation Guidelines for KeyStone I Devices
  PDF, 590 Kb, File published: Oct 31, 2012
  The goal of KeyStone I SerDes collateral material is to make system implementation easier for the customer by providing the system solution. For these SerDes-based interfaces, it is not assumed that the system designer is familiar with the industry specifications, SerDes technology, or RF/microwave PCB design. However, it is still expected that the PCB design work will be supervised by a knowledge
• Download
  KeyStone I DDR3 Initialization (Rev. E)
  PDF, 114 Kb, Revision: E, File published: Oct 28, 2016
  The initialization of the DDR3 DRAM controller on KeyStone I DSPs is straightforward as long as the proper steps are followed. However, if some steps are omitted or if some sequence-sensitive steps are implemented in the wrong order, DDR3 operation will be unpredictable.All DDR3 initialization routines must contain the basic register writes to configure the memory controller within the DSP
• Download
  TMS320C66x DSP Generation of Devices (Rev. A)
  PDF, 245 Kb, Revision: A, File published: Apr 25, 2011
• Download
  Hardware Design Guide for KeyStone Devices (Rev. C)
  PDF, 1.7 Mb, Revision: C, File published: Sep 15, 2013
• Download
  SERDES Link Commissioning on KeyStone I and II Devices
  PDF, 138 Kb, File published: Apr 13, 2016
  The serializer-deserializer (SerDes) performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the CPU. This application report explains the SerDes transmit and receive parameters tuning, tools and some debug techniques for TI Keystone I and Keystone II devices.
• Download
  PCIe Use Cases for KeyStone Devices
  PDF, 320 Kb, File published: Dec 13, 2011
• Download
  Clocking Design Guide for KeyStone Devices
  PDF, 1.5 Mb, File published: Nov 9, 2010
• Download
  The C6000 Embedded Application Binary Interface Migration Guide (Rev. A)
  PDF, 20 Kb, Revision: A, File published: Nov 10, 2010
  The C6000 compiler tools support a new ELF-based ABI named EABI. Prior to this time, the compiler only supported a single ABI, which is now named COFF ABI. The following compelling best-in-class features are available under the C6000 EABI:GeneralZero-init globals: “int gvar;” gets set to 0 before main runs.Dynamic linking: Add code to a running system.Native ROM
• Download
  Optimizing Loops on the C66x DSP
  PDF, 585 Kb, File published: Nov 9, 2010
• Download
  DDR3 Design Requirements for KeyStone Devices (Rev. B)
  PDF, 582 Kb, Revision: B, File published: Jun 5, 2014
• Download
  Multicore Programming Guide (Rev. B)
  PDF, 1.8 Mb, Revision: B, File published: Aug 29, 2012
  As application complexity continues to grow, we have reached a limit on increasing performance by merely scaling clock speed. To meet the ever-increasing processing demand, modern System-On-Chip solutions contain multiple processing cores. The dilemma is how to map applications to multicore devices. In this paper, we present a programming methodology for converting applications to run on multicore

Model Line

Manufacturer's Classification

• Semiconductors > Processors > Digital Signal Processors > C6000 DSP > C66x DSP