Datasheet Texas Instruments CD74HC74M96
Manufacturer | Texas Instruments |
Series | CD74HC74 |
Part Number | CD74HC74M96 |
High Speed CMOS Logic Dual Positive-Edge-Triggered D-Type Flip-Flops with Set and Reset 14-SOIC -55 to 125
Datasheets
CD54HC74, CD74HC74, CD54HCT74, CD74HCT74 datasheet
PDF, 727 Kb, Revision: D, File published: Aug 21, 2003
Extract from the document
Prices
Status
Lifecycle Status | Active (Recommended for new designs) |
Manufacture's Sample Availability | No |
Packaging
Pin | 14 |
Package Type | D |
Industry STD Term | SOIC |
JEDEC Code | R-PDSO-G |
Package QTY | 2500 |
Carrier | LARGE T&R |
Device Marking | HC74M |
Width (mm) | 3.91 |
Length (mm) | 8.65 |
Thickness (mm) | 1.58 |
Pitch (mm) | 1.27 |
Max Height (mm) | 1.75 |
Mechanical Data | Download |
Parametrics
3-State Output | No |
Bits | 2 |
F @ Nom Voltage(Max) | 28 Mhz |
ICC @ Nom Voltage(Max) | 0.04 mA |
Operating Temperature Range | -55 to 125 C |
Output Drive (IOL/IOH)(Max) | 5.2/-5.2 mA |
Package Group | SOIC |
Package Size: mm2:W x L | 14SOIC: 52 mm2: 6 x 8.65(SOIC) PKG |
Rating | Catalog |
Schmitt Trigger | No |
Technology Family | HC |
VCC(Max) | 6 V |
VCC(Min) | 2 V |
Voltage(Nom) | 3.3,5 V |
tpd @ Nom Voltage(Max) | 37 ns |
Eco Plan
RoHS | Compliant |
Application Notes
- Power-Up Behavior of Clocked Devices (Rev. A)PDF, 34 Kb, Revision: A, File published: Feb 6, 2015
- SN54/74HCT CMOS Logic Family Applications and RestrictionsPDF, 102 Kb, File published: May 1, 1996
The TI SN54/74HCT family of CMOS devices is a subgroup of the SN74HC series with the HCT circuitry modified to meet the interfacing requirements of TTL outputs to high-speed CMOS inputs. The HCT devices can be driven by the TTL circuits directly without additional components. This document describes the TTL/HC interface the operating voltages circuit noise and power consumption. A Bergeron anal
Model Line
Series: CD74HC74 (10)
Manufacturer's Classification
- Semiconductors > Logic > Flip-Flop/Latch/Register > D-Type Flip-Flop