Datasheet Texas Instruments CD74AC74E
Manufacturer | Texas Instruments |
Series | CD74AC74 |
Part Number | CD74AC74E |
Dual Positive-Edge-Triggered D-Type Flip-Flops with Set and Reset 14-PDIP -55 to 125
Datasheets
CD54AC74, CD74AC74 datasheet
PDF, 786 Kb, Revision: D, File published: Dec 5, 2002
Extract from the document
Prices
Status
Lifecycle Status | Active (Recommended for new designs) |
Manufacture's Sample Availability | No |
Packaging
Pin | 14 |
Package Type | N |
Industry STD Term | PDIP |
JEDEC Code | R-PDIP-T |
Package QTY | 25 |
Carrier | TUBE |
Device Marking | CD74AC74E |
Width (mm) | 6.35 |
Length (mm) | 19.3 |
Thickness (mm) | 3.9 |
Pitch (mm) | 2.54 |
Max Height (mm) | 5.08 |
Mechanical Data | Download |
Parametrics
3-State Output | No |
Bits | 2 |
F @ Nom Voltage(Max) | 100 Mhz |
ICC @ Nom Voltage(Max) | 0.04 mA |
Operating Temperature Range | -55 to 125 C |
Output Drive (IOL/IOH)(Max) | 24/-24 mA |
Package Group | PDIP |
Package Size: mm2:W x L | See datasheet (PDIP) PKG |
Rating | Catalog |
Schmitt Trigger | No |
Technology Family | AC |
VCC(Max) | 5.5 V |
VCC(Min) | 1.5 V |
Voltage(Nom) | 1.5,3.3,5 V |
tpd @ Nom Voltage(Max) | 114,12.7,9.1 ns |
Eco Plan
RoHS | Compliant |
Pb Free | Yes |
Application Notes
- Power-Up Behavior of Clocked Devices (Rev. A)PDF, 34 Kb, Revision: A, File published: Feb 6, 2015
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple VccPDF, 43 Kb, File published: Apr 1, 1996
Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren
Model Line
Series: CD74AC74 (8)
Manufacturer's Classification
- Semiconductors > Logic > Flip-Flop/Latch/Register > D-Type Flip-Flop