Datasheet Texas Instruments CD4020BNSRG4

ManufacturerTexas Instruments
SeriesCD4020B
Part NumberCD4020BNSRG4
Datasheet Texas Instruments CD4020BNSRG4

CMOS 14-Stage Ripple-Carry Binary Counter/Divider 16-SO -55 to 125

Datasheets

Datasheet CD4020B, CD4024B, CD4040B
PDF, 1.6 Mb, Revision: D, File published: Dec 11, 2003, Pages: 25
CMOS Ripple-Carry Binary Counter/Dividers
Extract from the document

Prices

Status

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

Packaging

Pin16
Package TypeNS
Industry STD TermSOP
JEDEC CodeR-PDSO-G
Package QTY2000
CarrierLARGE T&R
Device MarkingCD4020B
Width (mm)5.3
Length (mm)10.3
Thickness (mm)1.95
Pitch (mm)1.27
Max Height (mm)2
Mechanical DataDownload

Parametrics

Approx. price0.11 | 1ku US$
Bits12
F @ nom voltage(Max)8 MHz
FunctionCounter
ICC @ nom voltage(Max)0.03 mA
IOH(Max)-1.5 mA
IOL(Max)1.5 mA
Operating temperature range-55 to 125 C
Package GroupPDIP|16,SO|16,TSSOP|16
Package size: mm2:W x LSee datasheet (PDIP),16SO: 80 mm2: 7.8 x 10.2 (SO|16),16TSSOP: 22 mm2: 4.4 x 5 (TSSOP|16) PKG
RatingCatalog
Technology FamilyCD4000
TypeBinary
VCC(Max)18 V
VCC(Min)3 V
Voltage(Nom)5,10,15 V
tpd @ nom Voltage(Max)160 ns

Eco Plan

RoHSCompliant
Pb FreeYes

Design Kits & Evaluation Modules

  • Evaluation Modules & Boards: 14-24-LOGIC-EVM
    Generic Logic EVM Supporting 14 through 24 Pin PW; DB; D; DW; NS; P; N; and DGV Packages
    Lifecycle Status: Active (Recommended for new designs)

Application Notes

  • Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics
    PDF, 188 Kb, File published: Dec 3, 2001
    Both buffered and unbuffered CMOS B-series gates inverters and high-current IC products are available from TI. Each product classification has application advantages in appropriate logic-system designs. Many CMOS suppliers have concentrated on promoting buffered B-series products with applications literature focusing on the attributes and use of the buffered types. This practice has left an imb
  • Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
    PDF, 337 Kb, File published: Jul 8, 2004
    Forty-eight-pin TSSOP components that were packaged using Texas Instruments (TI) standard packing methodology were subjected to electrical discharges between 0.5 and 20 kV as generated by an IEC ESD simulator to determine the level of ISD protection provided by the packing materials. The testing included trays tape and reel and magazines. Additional units were subjected to the same discharge
  • Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
    PDF, 614 Kb, Revision: C, File published: Dec 2, 2015

Model Line

Manufacturer's Classification

  • Semiconductors > Logic > Specialty logic > Counter/arithmetic/parity function