Datasheet Texas Instruments CD4072B

ManufacturerTexas Instruments
SeriesCD4072B
Datasheet Texas Instruments CD4072B

CMOS Dual 4-Input OR Gate

Datasheets

CD4071B, CD4072B, CD4075B TYPES datasheet
PDF, 1.7 Mb, Revision: D, File published: Aug 21, 2003
Extract from the document

Prices

Status

CD4072BECD4072BEE4CD4072BMCD4072BM96CD4072BM96G4CD4072BME4CD4072BMTCD4072BNSRCD4072BNSRE4CD4072BNSRG4CD4072BPWCD4072BPWG4
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityYesYesNoNoNoNoYesNoYesYesNoNo

Packaging

CD4072BECD4072BEE4CD4072BMCD4072BM96CD4072BM96G4CD4072BME4CD4072BMTCD4072BNSRCD4072BNSRE4CD4072BNSRG4CD4072BPWCD4072BPWG4
N123456789101112
Pin141414141414141414141414
Package TypeNNDDDDDNSNSNSPWPW
Industry STD TermPDIPPDIPSOICSOICSOICSOICSOICSOPSOPSOPTSSOPTSSOP
JEDEC CodeR-PDIP-TR-PDIP-TR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY25255025002500502502000200020009090
CarrierTUBETUBETUBELARGE T&RLARGE T&RTUBESMALL T&RLARGE T&RLARGE T&RLARGE T&RTUBETUBE
Device MarkingCD4072BECD4072BECD4072BMCD4072BMCD4072BMCD4072BMCD4072BMCD4072BCD4072BCD4072BCM072BCM072B
Width (mm)6.356.353.913.913.913.913.915.35.35.34.44.4
Length (mm)19.319.38.658.658.658.658.6510.310.310.355
Thickness (mm)3.93.91.581.581.581.581.581.951.951.9511
Pitch (mm)2.542.541.271.271.271.271.271.271.271.270.650.65
Max Height (mm)5.085.081.751.751.751.751.752221.21.2
Mechanical DataDownloadDownloadDownloadDownloadDownloadDownloadDownloadDownloadDownloadDownloadDownloadDownload

Parametrics

Parameters / ModelsCD4072BE
CD4072BE
CD4072BEE4
CD4072BEE4
CD4072BM
CD4072BM
CD4072BM96
CD4072BM96
CD4072BM96G4
CD4072BM96G4
CD4072BME4
CD4072BME4
CD4072BMT
CD4072BMT
CD4072BNSR
CD4072BNSR
CD4072BNSRE4
CD4072BNSRE4
CD4072BNSRG4
CD4072BNSRG4
CD4072BPW
CD4072BPW
CD4072BPWG4
CD4072BPWG4
Bits222222222222
F @ Nom Voltage(Max), Mhz888888888888
ICC @ Nom Voltage(Max), mA0.0150.0150.0150.0150.0150.0150.0150.0150.0150.0150.0150.015
IOH(Max), mA-1.5-1.5-1.5-1.5-1.5-1.5-1.5-1.5-1.5-1.5-1.5-1.5
IOL(Max), mA1.51.51.51.51.51.51.51.51.51.51.51.5
Operating Temperature Range, C-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125
Package GroupPDIPPDIPSOICSOICSOICSOICSOICSOSOSOTSSOPTSSOP
Package Size: mm2:W x L, PKGSee datasheet (PDIP)See datasheet (PDIP)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SO: 80 mm2: 7.8 x 10.2(SO)14SO: 80 mm2: 7.8 x 10.2(SO)14SO: 80 mm2: 7.8 x 10.2(SO)14TSSOP: 32 mm2: 6.4 x 5(TSSOP)14TSSOP: 32 mm2: 6.4 x 5(TSSOP)
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNoNoNoNoNoNoNoNo
Technology FamilyCD4000CD4000CD4000CD4000CD4000CD4000CD4000CD4000CD4000CD4000CD4000CD4000
VCC(Max), V181818181818181818181818
VCC(Min), V333333333333
Voltage(Nom), V101010101010101010101010
tpd @ Nom Voltage(Max), ns120120120120120120120120120120120120

Eco Plan

CD4072BECD4072BEE4CD4072BMCD4072BM96CD4072BM96G4CD4072BME4CD4072BMTCD4072BNSRCD4072BNSRE4CD4072BNSRG4CD4072BPWCD4072BPWG4
RoHSCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliant
Pb FreeYesYes

Application Notes

  • Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics
    PDF, 188 Kb, File published: Dec 3, 2001
    Both buffered and unbuffered CMOS B-series gates inverters and high-current IC products are available from TI. Each product classification has application advantages in appropriate logic-system designs. Many CMOS suppliers have concentrated on promoting buffered B-series products with applications literature focusing on the attributes and use of the buffered types. This practice has left an imb
  • Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
    PDF, 337 Kb, File published: Jul 8, 2004
    Forty-eight-pin TSSOP components that were packaged using Texas Instruments (TI) standard packing methodology were subjected to electrical discharges between 0.5 and 20 kV as generated by an IEC ESD simulator to determine the level of ISD protection provided by the packing materials. The testing included trays tape and reel and magazines. Additional units were subjected to the same discharge
  • Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
    PDF, 614 Kb, Revision: C, File published: Dec 2, 2015
  • Introduction to Logic
    PDF, 93 Kb, File published: Apr 30, 2015

Model Line

Manufacturer's Classification

  • Semiconductors > Logic > Gate > OR Gate