Datasheet LTC3896 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 150V Low IQ, Synchronous Inverting DC/DC Controller |
| Pages / Page | 36 / 9 — pin FuncTions OVLO (Pin 1):. VFB (Pin 6):. ITH (Pin 7):. VPRG (Pin 2):. … |
| File Format / Size | PDF / 2.0 Mb |
| Document Language | English |
pin FuncTions OVLO (Pin 1):. VFB (Pin 6):. ITH (Pin 7):. VPRG (Pin 2):. MODE (Pin 8):. SENSE+ (Pin 3):
Model Line for this Datasheet
Text Version of Document
link to page 16 LTC3896
pin FuncTions OVLO (Pin 1):
Overvoltage Lockout Input. A voltage on this
VFB (Pin 6):
Feedback Input. If the VPRG pin is floating, pin above 1.2V with respect to V – OUT disables switching the VFB pin receives the remotely sensed feedback voltage of the controller. The DRVCC and INTVCC supplies maintain from an external resistor divider across the output. If VPRG regulation during an OVLO event. Exceeding the OVLO is tied to V – OUT or INTVCC, the VFB pin should connect to threshold triggers a soft-start reset. If the OVLO function the GND pin. is not used, connect this pin to V – OUT .
ITH (Pin 7):
Error Amplifier Output and Switching Regulator
VPRG (Pin 2):
Output Voltage Control Pin. This pin sets Compensation Point. The current comparator trip point the regulator in adjustable output mode using external increases with this control voltage. feedback resistors or fixed –5V/–3.3V output mode.
MODE (Pin 8):
Mode Select and Burst Clamp Adjust Floating this pin allows the output to be programmed from Input. This input determines how the LTC3896 operates –0.8V to –60V with an external resistor divider on the VFB at light loads. Pulling this pin to V – selects Burst pin, regulating V – OUT FB to 0.8V with respect to VOUT . Tying Mode operation with the burst clamp level defaulting to this pin to INTV – CC or VOUT programs the output to –5V or 25% of V –3.3V, respectively, through an internal resistor divider on SENSE(MAX). Tying this pin to a voltage between 0.5V and 1.0V with respect to V – selects Burst Mode V OUT FB. In fixed –5V/–3.3V output mode, VFB should connect operation and adjusts the burst clamp between 10% and to GND, which is the positive terminal of the output. 60%. Tying this pin to INTVCC forces continuous inductor
SENSE+ (Pin 3):
The (+) Input to the Differential Current current operation. Tying this pin to a voltage greater than Comparator. The ITH pin voltage and controlled offsets 1.4V and less than INTV – CC–1.3V (with respect to VOUT ) between the SENSE– and SENSE+ pins in conjunction with selects pulse-skipping operation. RSENSE set the current trip threshold.
V – OUT (Pins 9, 15, Exposed Pin 39):
Negative Terminal of
SENSE– (Pin 4):
The (–) Input to the Differential Current Output Voltage. This serves as a virtual ground return for Comparator. When SENSE– is greater than INTVCC, the most of the LTC3896’s circuits. Most pins and components SENSE– pin supplies power to the current comparator. are referenced to V – OUT , which can operate at up to 60V
SS (Pin 5):
Soft-Start Input. The LTC3896 regulates the (65V Abs Max) below the GND pin. The exposed pad must V – be soldered to the PCB for rated electrical and thermal FB voltage with respect to VOUT to the smaller of 0.8V or the voltage on the SS pin. An internal 10μA pull-up current performance. source is connected to this pin. A capacitor to V –
–
OUT at this
VOUT (Pin 10):
This pin must be externally tied to the other pin sets the ramp time to final regulated output voltage. The V – OUT pins (Pin 9, e.g.) but is not internally electrically SS pin is also used for the Regulator Shutdown (REGSD) connected to them. feature. A 5μA/1μA pull-down current can be connected
CLKOUT (Pin 11):
Output Clock Signal. This signal is on SS depending on the state of the EXTVCC LDO and available to daisy-chain other controller ICs for additional the voltage on SS. See Regulator Shutdown (REGSD) MOSFET driver stages/phases. The output levels swing section in the Operation section for more information. from INTV –. To defeat the REGSD feature, place a 330kΩ or smaller CC to VOUT resistor between INTVCC and SS. See Soft-Start Pin in the
GND (Pin 12):
Ground. This pin should be externally tied Applications Information section for more information on to the true ground (e.g., ground terminal of the positive defeating REGSD. input supply connected to VIN). The RUN, PLLIN, and PGOOD pins are referenced to this GND pin. 3896f For more information www.linear.com/LTC3896 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts
pin FuncTions OVLO (Pin 1):
Overvoltage Lockout Input. A voltage on this
VFB (Pin 6):
Feedback Input. If the VPRG pin is floating, pin above 1.2V with respect to V – OUT disables switching the VFB pin receives the remotely sensed feedback voltage of the controller. The DRVCC and INTVCC supplies maintain from an external resistor divider across the output. If VPRG regulation during an OVLO event. Exceeding the OVLO is tied to V – OUT or INTVCC, the VFB pin should connect to threshold triggers a soft-start reset. If the OVLO function the GND pin. is not used, connect this pin to V – OUT .
ITH (Pin 7):
Error Amplifier Output and Switching Regulator
VPRG (Pin 2):
Output Voltage Control Pin. This pin sets Compensation Point. The current comparator trip point the regulator in adjustable output mode using external increases with this control voltage. feedback resistors or fixed –5V/–3.3V output mode.
MODE (Pin 8):
Mode Select and Burst Clamp Adjust Floating this pin allows the output to be programmed from Input. This input determines how the LTC3896 operates –0.8V to –60V with an external resistor divider on the VFB at light loads. Pulling this pin to V – selects Burst pin, regulating V – OUT FB to 0.8V with respect to VOUT . Tying Mode operation with the burst clamp level defaulting to this pin to INTV – CC or VOUT programs the output to –5V or 25% of V –3.3V, respectively, through an internal resistor divider on SENSE(MAX). Tying this pin to a voltage between 0.5V and 1.0V with respect to V – selects Burst Mode V OUT FB. In fixed –5V/–3.3V output mode, VFB should connect operation and adjusts the burst clamp between 10% and to GND, which is the positive terminal of the output. 60%. Tying this pin to INTVCC forces continuous inductor
SENSE+ (Pin 3):
The (+) Input to the Differential Current current operation. Tying this pin to a voltage greater than Comparator. The ITH pin voltage and controlled offsets 1.4V and less than INTV – CC–1.3V (with respect to VOUT ) between the SENSE– and SENSE+ pins in conjunction with selects pulse-skipping operation. RSENSE set the current trip threshold.
V – OUT (Pins 9, 15, Exposed Pin 39):
Negative Terminal of
SENSE– (Pin 4):
The (–) Input to the Differential Current Output Voltage. This serves as a virtual ground return for Comparator. When SENSE– is greater than INTVCC, the most of the LTC3896’s circuits. Most pins and components SENSE– pin supplies power to the current comparator. are referenced to V – OUT , which can operate at up to 60V
SS (Pin 5):
Soft-Start Input. The LTC3896 regulates the (65V Abs Max) below the GND pin. The exposed pad must V – be soldered to the PCB for rated electrical and thermal FB voltage with respect to VOUT to the smaller of 0.8V or the voltage on the SS pin. An internal 10μA pull-up current performance. source is connected to this pin. A capacitor to V –
–
OUT at this
VOUT (Pin 10):
This pin must be externally tied to the other pin sets the ramp time to final regulated output voltage. The V – OUT pins (Pin 9, e.g.) but is not internally electrically SS pin is also used for the Regulator Shutdown (REGSD) connected to them. feature. A 5μA/1μA pull-down current can be connected
CLKOUT (Pin 11):
Output Clock Signal. This signal is on SS depending on the state of the EXTVCC LDO and available to daisy-chain other controller ICs for additional the voltage on SS. See Regulator Shutdown (REGSD) MOSFET driver stages/phases. The output levels swing section in the Operation section for more information. from INTV –. To defeat the REGSD feature, place a 330kΩ or smaller CC to VOUT resistor between INTVCC and SS. See Soft-Start Pin in the
GND (Pin 12):
Ground. This pin should be externally tied Applications Information section for more information on to the true ground (e.g., ground terminal of the positive defeating REGSD. input supply connected to VIN). The RUN, PLLIN, and PGOOD pins are referenced to this GND pin. 3896f For more information www.linear.com/LTC3896 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts
