Datasheet ADA4841-1, ADA4841-2 (Analog Devices) - 6

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ADA4841-1/ADA4841-2 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 4.
PD = Quiescent Power + (Total Drive Power − Load Power)
Parameter Rating
 V V  V 2 Supply Voltage 12.6 V P  V  I  S OUT OUT    D S S   2 R R Power Dissipation See Figure 5  L  L Common-Mode Input Voltage −VS − 0.5 V to +VS + 0.5 V RMS output voltages should be considered. If RL is referenced Differential Input Voltage 1.8 V to −VS, as in single-supply operation, the total drive power is Storage Temperature Range −65°C to +125°C VS × IOUT. If the rms signal levels are indeterminate, consider the Operating Temperature Range −40°C to +125°C worst case, when VOUT = VS/4 for RL to midsupply. Lead Temperature JEDEC J-STD-20 2 Junction Temperature 150°C V /4    D P  S V IS   S  RL Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a In single-supply operation with RL referenced to −VS, worst case stress rating only; functional operation of the product at these is VOUT = VS/2. or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond Airflow increases heat dissipation, effectively reducing θJA. the maximum operating conditions for extended periods may In addition, more metal directly in contact with the package affect product reliability. leads and through holes under the device reduces θJA.
THERMAL RESISTANCE
Figure 5 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 8-lead SOIC_N θJA is specified for the worst-case conditions, that is, θJA is (125°C/W), the 6-lead SOT-23 (170°C/W), 8-lead MSOP specified for device soldered in circuit board for surface-mount (145°C/W), and 8-lead LFCSP_WD (103°C/W) on a JEDEC packages. standard 4-layer board. θJA values are approximations.
Table 5. Thermal Resistance 2.0 Package Type θJA Unit
8-lead SOIC_N 125 °C/W
) LFCSP
6-Lead SOT-23 170 °C/W
(W N 1.5
8-lead MSOP 130 °C/W
IO T A
8-Lead LFCSP_WD 103 °C/W
IP SOIC ISS D MSOP MAXIMUM POWER DISSIPATION R 1.0 E W
The maximum safe power dissipation for the ADA4841-1/
PO SOT-23 M
ADA4841-2 is limited by the associated rise in junction
IMU 0.5 X
temperature (TJ) on the die. At approximately 150C, which is
MA
the glass transition temperature, the plastic changes its 61 0 4- properties. Even temporarily exceeding this temperature limit 61
0
05 may change the stresses that the package exerts on the die,
–55 –45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85 95 105 115 125 AMBIENT TEMPERATURE (°C)
permanently shifting the parametric performance of the Figure 5. Maximum Power Dissipation vs. Temperature for a 4-Layer Board amplifiers. Exceeding a junction temperature of 150°C for an extended period can result in changes in silicon devices, potentially causing degradation or loss of functionality.
ESD CAUTION
The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the die due to the amplifier’s drive at the output. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Rev. G | Page 6 of 20 Document Outline FEATURES APPLICATIONS CONNECTION DIAGRAMS GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION AMPLIFIER DESCRIPTION DC ERRORS NOISE CONSIDERATIONS HEADROOM CONSIDERATIONS CAPACITANCE DRIVE INPUT PROTECTION POWER-DOWN OPERATION APPLICATIONS INFORMATION TYPICAL PERFORMANCE VALUES 16-BIT ADC DRIVER RECONSTRUCTION FILTER LAYOUT CONSIDERATIONS GROUND PLANE POWER SUPPLY BYPASSING OUTLINE DIMENSIONS ORDERING GUIDE