Datasheet AD8099 (Analog Devices) - 25

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Data Sheet AD8099 CIRCUIT CONSIDERATIONS
used, they should be stitched together with multiple vias. The Optimizing the performance of the AD8099 requires attention returns for the input, output terminations, bypass capacitors, and to detail in layout and signal routing of the board. Power supply RG should all be kept as close to the AD8099 as possible. Ground bypassing, parasitic capacitance, and component selection all vias should be placed at the very end of the component mounting contribute to the overal performance of the amplifier. The pad to provide a solid ground return. The output load ground and AD8099 features an exposed paddle on the backs of both the the bypass capacitor grounds should be returned to a common LFCSP and SOIC packages. The exposed paddle provides a low point on the ground plane to minimize parasitic inductance and thermal resistive path to the ground plane. For best performance, improve distortion performance. The AD8099 packages feature solder the exposed paddle to the ground plane. an exposed paddle. For optimum performance, solder this paddle to ground. For more information on PCB layout and
PCB Layout
design considerations, refer to section 7-2 of the 2002 Analog The compensation network is determined by the amplifier Devices Op Amp Applications book. gain requirements. For lower gains, the layout and component placement are more critical. For higher gains, there are fewer
Power Supply Bypassing
compensation components, which results in a less complex The AD8099 power supply bypassing has been optimized layout. for each gain configuration as shown in Figure 60 through
Parasitics
Figure 66 in the Circuit Configurations section. The values shown should be used when possible. Bypassing is critical for The area surrounding the compensation pin is very sensitive to stability, frequency response, distortion, and PSRR performance. parasitic capacitance. To realize the ful gain bandwidth product The 0.1 µF capacitors shown in Figure 60 through Figure 66 of the AD8099, there should be no trace connected to or within should be as close to the supply pins of the AD8099 as possible close proximity of the external compensation pin for the lowest and the electrolytic capacitors beside them. possible capacitance. When compensation is required, the traces to the compensation pin, the negative supply, and the interconnect
Component Selection
between components (CC, C1, and RC in Figure 59) should be Smaller components less than 1206 SMT case size, offer smaller made as wide as possible to minimize inductance. mounting pads, which have fewer parasitics and al ow for a more All ground and power planes under the pins of the AD8099 compact layout. It is critical for optimum performance that high should be cleared of copper to prevent parasitic capacitance quality, tight tolerance (where critical), and low drift components between the input and output pins to ground. A single mount- be used. For example, tight tolerance and low drift is critical in ing pad on a SOIC footprint can add as much as 0.2 pF of the selection of the feedback capacitor used in Figure 60. The capacitance to ground as a result of not clearing the ground or feedback compensation capacitor in Figure 60 is 1.5 pF. This power plane under the AD8099 pins. Parasitic capacitance can capacitor should be specified with NPO material. NPO material cause peaking and instability, and should be minimized to typically has a ±30 ppm/°C change over −55°C to +125°C ensure proper operation. temperature range. For a 100°C change, this results in a 4.5 fF change in capacitance, compared to an X7R material, which The new pinout of the AD8099 reduces the distance between results in a 0.23 pF change, a 15% change from the nominal value. the output and the inverting input of the amplifier. This helps This can introduce excessive peaking, as shown in Figure 71. to minimize the parasitic inductance and capacitance of the feedback path, which, in turn, reduces ringing and second
DESIGN TOOLS AND TECHNICAL SUPPORT
harmonic distortion. Analog Devices is committed to the design process by providing
Grounding
technical support and online design tools. Analog Devices When possible, ground and power planes should be used. Ground offers technical support via evaluation boards, sample ICs, and power planes reduce the resistance and inductance of the SPICE models, interactive evaluation tools, application notes, power supply feeds and ground returns. If multiple planes are phone and email support—all available at www.analog.com. Rev. E | Page 23 of 26 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION CONNECTION DIAGRAMS REVISION HISTORY SPECIFICATIONS SPECIFICATIONS WITH ±5 V SUPPLY SPECIFICATIONS WITH +5 V SUPPLY ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION USING THE AD8099 CIRCUIT COMPONENTS RECOMMENDED VALUES CIRCUIT CONFIGURATIONS PERFORMANCE vs. COMPONENT VALUES TOTAL OUTPUT NOISE CALCULATIONS AND DESIGN INPUT BIAS CURRENT AND DC OFFSET PIN AND INPUT BIAS CANCELLATION 16-BIT ADC DRIVER CIRCUIT CONSIDERATIONS PCB Layout Parasitics Grounding Power Supply Bypassing Component Selection DESIGN TOOLS AND TECHNICAL SUPPORT OUTLINE DIMENSIONS ORDERING GUIDE