Datasheet AD8038, AD8039 (Analog Devices) - 5

link to page 5 link to page 13 link to page 5
AD8038/AD8039 ABSOLUTE MAXIMUM RATINGS 2.0 Table 3. ) Parameter Rating (W
Supply Voltage 12.6 V
N 1.5 IO T SOIC-8
Power Dissipation See Figure 5
IPA
Common-Mode Input Voltage ±V
S
S
IS SOT-23-8 D
Differential Input Voltage ±4 V
R 1.0 E
Storage Temperature Range −65°C to +125°C
W SC70-5 O
Operating Temperature Range −40°C to +85°C
M P
Lead Temperature (Soldering, 10 sec) 300°C
MU 0.5 XI MA
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
0
5
–55 –25 5 35 65 95 125
00 1- rating only; functional operation of the device at these or any
AMBIENT TEMPERATURE (°C)
95 02 other conditions above those indicated in the operational Figure 5. Maximum Power Dissipation vs. Temperature for a 4-Layer Board section of this specification is not implied. Exposure to absolute RMS output voltages should be considered. If RL is referenced to maximum rating conditions for extended periods may affect VS−, as in single-supply operation, then the total drive power is device reliability. VS × IOUT. If the rms signal levels are indeterminate, consider the
MAXIMUM POWER DISSIPATION
worst case, when VOUT = VS /4 for RL to midsupply The maximum safe power dissipation in the AD8038/AD8039 PD = (VS × IS) + (VS/4)2/RL package is limited by the associated rise in junction temperature In single-supply operation with RL referenced to VS−, worst case (TJ) on the die. The plastic encapsulating the die locally reaches is VOUT = VS /2. the junction temperature. At approximately 150°C, which is the Airflow increases heat dissipation, effectively reducing θ glass transition temperature, the plastic changes its properties. JA. In addition, more metal directly in contact with the package leads Even temporarily exceeding this temperature limit may change from metal traces, throughholes, ground, and power planes reduce the stresses that the package exerts on the die, permanently the θ shifting the parametric performance of the AD8038/AD8039. JA. Care must be taken to minimize parasitic capacitances at the input leads of high speed op amps as discussed in the Exceeding a junction temperature of 175°C for an extended Layout, Grounding, and Bypassing Considerations section. time can result in changes in the silicon devices, potentially causing failure. Figure 5 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 8-lead SOIC The still-air thermal properties of the package and PCB (θJA), (125°C/W), 5-lead SC70 (210°C/W), and 8-lead SOT-23 ambient temperature (TA), and total power dissipated in the (160°C/W) packages on a JEDEC standard 4-layer board. package (PD) determine the junction temperature of the die. θ The junction temperature can be calculated as JA values are approximations.
OUTPUT SHORT CIRCUIT
TJ = TA + (PD × θJA) Shorting the output to ground or drawing excessive current The power dissipated in the package (PD) is the sum of the from the AD8038/AD8039 will likely cause a catastrophic failure. quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) multiplied by the
ESD CAUTION
quiescent current (IS). Assuming the load (RL) is referenced to midsupply, then the total drive power is VS/2 × IOUT, some of which is dissipated in the package and some in the load (VOUT × IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package. PD = quiescent power + (total drive power − load power) P 2 D = [VS × IS] + [(VS/2) × (VOUT/RL)] − [VOUT /RL] Rev. G | Page 5 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION OUTPUT SHORT CIRCUIT ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS DISABLE POWER SUPPLY BYPASSING GROUNDING INPUT CAPACITANCE OUTPUT CAPACITANCE INPUT-TO-OUTPUT COUPLING APPLICATIONS INFORMATION LOW POWER ADC DRIVER LOW POWER ACTIVE VIDEO FILTER OUTLINE DIMENSIONS ORDERING GUIDE