Datasheet LTC1272 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 12-Bit, 3µs, 250kHz Sampling A/D Converter |
| Pages / Page | 22 / 9 — APPLICATIONS INFORMATION. Signal-to-Noise Ratio. Effective Number of … |
| File Format / Size | PDF / 297 Kb |
| Document Language | English |
APPLICATIONS INFORMATION. Signal-to-Noise Ratio. Effective Number of Bits. Figure 4. LTC1272 Dynamic DNL. fCLK = 4MHz,
Model Line for this Datasheet
- LTC1272-3ACN#PBF LTC1272-3ACSW#PBF LTC1272-3ACSW#TRPBF LTC1272-3CCN#PBF LTC1272-3CCSW#PBF LTC1272-3CCSW#TRPBF LTC1272-8ACN#PBF LTC1272-8ACSW#PBF LTC1272-8ACSW#TRPBF LTC1272-8CCN#PBF LTC1272-8CCSW#PBF LTC1272-8CCSW#TRPBF
Text Version of Document
LTC1272
APPLICATIONS INFORMATION Signal-to-Noise Ratio
1.0 The Signal-to-Noise Ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency to 0.5 the RMS amplitude of all other frequency components at the A/D output. This includes distortion as well as noise 0 products and for this reason it is sometimes referred to as Signal-to-Noise + Distortion [S/(N + D)]. The output is band ERROR (LSB) limited to frequencies from DC to one half the sampling –0.5 frequency. Figure 2 shows spectral content from DC to 125kHz which is 1/2 the 250kHz sampling rate. –1.0 0 1 2 3 4
Effective Number of Bits
CODE (THOUSANDS) LTC1272 • F04 The effective number of bits (ENOBs) is a measurement
Figure 4. LTC1272 Dynamic DNL. fCLK = 4MHz,
of the resolution of an A/D and is directly related to the
fS = 250kHz, fIN = 122.25342kHz, VCC = 5V
S/(N + D) by the equation: N = [S/(N + D) –1.76]/6.02
Total Harmonic Distortion
where N is the effective number of bits of resolution and Total Harmonic Distortion (THD) is the ratio of the RMS S/(N + D) is expressed in dB. At the maximum sampling sum of all harmonics of the input signal to the fundamental rate of 250kHz the LTC1272 maintains 11.5 ENOBs or bet- itself. The harmonics are limited to the frequency band ter to 20kHz. Above 20kHz the ENOBs gradually decline, between DC and one half the sampling frequency. THD is as shown in Figure 3, due to increasing second harmonic expressed as: 20 LOG [√V22 + V32 + ... + VN2 / V1] where distortion. The noise floor remains approximately 90dB. V1 is the RMS amplitude of the fundamental frequency and The dynamic differential nonlinearity remains good out to V2 through VN are the amplitudes of the second through 120kHz as shown in Figure 4. Nth harmonics.
Clock and Control Synchronization
12 For best analog performance, the LTC1272 clock should be 11 synchronized to the CS and RD control inputs as shown in 10 9 Figure 5, with at least 40ns separating convert start from 8 the nearest CLK IN edge. This ensures that transitions at 7 CLK IN and CLK OUT do not couple to the analog input 6 ENOBs* and get sampled by the sample-and-hold. The magnitude 5 4 of this feedthrough is only a few millivolts, but if CLK and 3 convert start (CS and RD) are asynchronous, frequency 2 fS = 250kHz components caused by mixing the clock and convert 1 VDD = 5V 0 signals may increase the apparent input noise. 0 20 40 60 80 100 120 When the clock and convert signals are synchronized, fIN (kHz) LT1272 • F03 small endpoint errors (offset and full-scale) are the most that can be generated by clock feedthrough. Even these
Figure 3. LTC1272 Effective Number of Bits (ENOBs) vs Input
errors (which can be trimmed out) can be eliminated
Frequency. fS = 250kHz
by ensuring that the start of a conversion (CS and RD’s falling edge) does not occur within 40ns of a clock edge, 1272fc For more information www.linear.com/1272 9 Document Outline FEATURES APPLICATIONS DESCRIPTION TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION CONVERTER CHARACTERISTICS INTERNAL REFERENCE CHARACTERISTICS DIGITAL AND DC ELECTRICAL CHARACTERISTICS DYNAMIC ACCURACY ANALOG INPUT TIMING CHARACTERISTICS PIN FUNCTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION REVISION HISTORY PACKAGE DESCRIPTION
APPLICATIONS INFORMATION Signal-to-Noise Ratio
1.0 The Signal-to-Noise Ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency to 0.5 the RMS amplitude of all other frequency components at the A/D output. This includes distortion as well as noise 0 products and for this reason it is sometimes referred to as Signal-to-Noise + Distortion [S/(N + D)]. The output is band ERROR (LSB) limited to frequencies from DC to one half the sampling –0.5 frequency. Figure 2 shows spectral content from DC to 125kHz which is 1/2 the 250kHz sampling rate. –1.0 0 1 2 3 4
Effective Number of Bits
CODE (THOUSANDS) LTC1272 • F04 The effective number of bits (ENOBs) is a measurement
Figure 4. LTC1272 Dynamic DNL. fCLK = 4MHz,
of the resolution of an A/D and is directly related to the
fS = 250kHz, fIN = 122.25342kHz, VCC = 5V
S/(N + D) by the equation: N = [S/(N + D) –1.76]/6.02
Total Harmonic Distortion
where N is the effective number of bits of resolution and Total Harmonic Distortion (THD) is the ratio of the RMS S/(N + D) is expressed in dB. At the maximum sampling sum of all harmonics of the input signal to the fundamental rate of 250kHz the LTC1272 maintains 11.5 ENOBs or bet- itself. The harmonics are limited to the frequency band ter to 20kHz. Above 20kHz the ENOBs gradually decline, between DC and one half the sampling frequency. THD is as shown in Figure 3, due to increasing second harmonic expressed as: 20 LOG [√V22 + V32 + ... + VN2 / V1] where distortion. The noise floor remains approximately 90dB. V1 is the RMS amplitude of the fundamental frequency and The dynamic differential nonlinearity remains good out to V2 through VN are the amplitudes of the second through 120kHz as shown in Figure 4. Nth harmonics.
Clock and Control Synchronization
12 For best analog performance, the LTC1272 clock should be 11 synchronized to the CS and RD control inputs as shown in 10 9 Figure 5, with at least 40ns separating convert start from 8 the nearest CLK IN edge. This ensures that transitions at 7 CLK IN and CLK OUT do not couple to the analog input 6 ENOBs* and get sampled by the sample-and-hold. The magnitude 5 4 of this feedthrough is only a few millivolts, but if CLK and 3 convert start (CS and RD) are asynchronous, frequency 2 fS = 250kHz components caused by mixing the clock and convert 1 VDD = 5V 0 signals may increase the apparent input noise. 0 20 40 60 80 100 120 When the clock and convert signals are synchronized, fIN (kHz) LT1272 • F03 small endpoint errors (offset and full-scale) are the most that can be generated by clock feedthrough. Even these
Figure 3. LTC1272 Effective Number of Bits (ENOBs) vs Input
errors (which can be trimmed out) can be eliminated
Frequency. fS = 250kHz
by ensuring that the start of a conversion (CS and RD’s falling edge) does not occur within 40ns of a clock edge, 1272fc For more information www.linear.com/1272 9 Document Outline FEATURES APPLICATIONS DESCRIPTION TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION CONVERTER CHARACTERISTICS INTERNAL REFERENCE CHARACTERISTICS DIGITAL AND DC ELECTRICAL CHARACTERISTICS DYNAMIC ACCURACY ANALOG INPUT TIMING CHARACTERISTICS PIN FUNCTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION REVISION HISTORY PACKAGE DESCRIPTION
