Datasheet LTC1289 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | 3 Volt Single Chip 12-Bit Data Acquisition System |
| Pages / Page | 28 / 3 — U W. CO VERTER A D ULTIPLEXER CHARACTERISTICS The. denotes the … |
| File Format / Size | PDF / 685 Kb |
| Document Language | English |
U W. CO VERTER A D ULTIPLEXER CHARACTERISTICS The. denotes the specifications
Model Line for this Datasheet
Text Version of Document
LTC1289
U U W CO VERTER A D ULTIPLEXER CHARACTERISTICS The
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 3) LTC1289B LTC1289C PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Minimum Resolution for ● 12 12 BITS Which No Missing Codes are Guaranteed Analog and REF Input Range (Note 7) (V–) – 0.05V to VCC + 0.05V (V–) – 0.05V to VCC + 0.05V V On Channel Leakage Current On Channel = 3V ● ±1 ±1 µA (Note 8) Off Channel = 0V On Channel = 0V ● ±1 ±1 µA Off Channel = 3V Off Channel Leakage Current On Channel = 3V ● ±1 ±1 µA (Note 8) Off Channel = 0V On Channel = 0V ● ±1 ±1 µA Off Channel = 3V
AC CHARACTERISTICS The
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 3) LTC1289B LTC1289C SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSCLK Shift Clock Frequency (Note 6) 0 1.0 MHz fACLK A/D Clock Frequency (Note 6) (Note 10) 2.0 MHz tACC Delay time from CS↓ to DOUT Data Valid (Note 9) 2 ACLK Cycles tSMPL Analog Input Sample Time See Operating Sequence 7 SCLK Cycles tCONV Conversion Time See Operating Sequence 52 ACLK Cycles tCYC Total Cycle Time See Operating Sequence (Note 6) 12 SCLK + Cycles 56 ACLK tdDO Delay Time, SCLK↓ to DOUT Data Valid See Test Circuits ● 200 350 ns tdis Delay Time, CS↑ to DOUT Hi-Z See Test Circuits ● 70 150 ns ten Delay Time, 2nd ACLK↓ to DOUT Enabled See Test Circuits ● 130 250 ns thCS Hold Time, CS After Last SCLK↓ (Note 6) 0 ns thDI Hold Time, DIN After SCLK↑ (Note 6) 50 ns thDO Time Output Data Remains Valid After SCLK↓ 50 ns tf DOUT Fall Time See Test Circuits ● 40 100 ns tr DOUT Rise Time See Test Circuits ● 40 100 ns tsuDI Setup Time, DIN Stable Before SCLK↑ (Note 6 and 9) 50 ns tsuCS Setup Time, CS↓ Before Clocking in (Note 6 and 9) 2 ACLK Cycles First Address Bit + 180ns tWHCS CS High Time During Conversion (Note 6) 52 ACLK Cycles CIN Input Capacitance Analog Inputs On Channel 100 pF Analog Inputs Off Channel 5 pF Digital Inputs 5 pF 1289fb 3
U U W CO VERTER A D ULTIPLEXER CHARACTERISTICS The
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 3) LTC1289B LTC1289C PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Minimum Resolution for ● 12 12 BITS Which No Missing Codes are Guaranteed Analog and REF Input Range (Note 7) (V–) – 0.05V to VCC + 0.05V (V–) – 0.05V to VCC + 0.05V V On Channel Leakage Current On Channel = 3V ● ±1 ±1 µA (Note 8) Off Channel = 0V On Channel = 0V ● ±1 ±1 µA Off Channel = 3V Off Channel Leakage Current On Channel = 3V ● ±1 ±1 µA (Note 8) Off Channel = 0V On Channel = 0V ● ±1 ±1 µA Off Channel = 3V
AC CHARACTERISTICS The
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 3) LTC1289B LTC1289C SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSCLK Shift Clock Frequency (Note 6) 0 1.0 MHz fACLK A/D Clock Frequency (Note 6) (Note 10) 2.0 MHz tACC Delay time from CS↓ to DOUT Data Valid (Note 9) 2 ACLK Cycles tSMPL Analog Input Sample Time See Operating Sequence 7 SCLK Cycles tCONV Conversion Time See Operating Sequence 52 ACLK Cycles tCYC Total Cycle Time See Operating Sequence (Note 6) 12 SCLK + Cycles 56 ACLK tdDO Delay Time, SCLK↓ to DOUT Data Valid See Test Circuits ● 200 350 ns tdis Delay Time, CS↑ to DOUT Hi-Z See Test Circuits ● 70 150 ns ten Delay Time, 2nd ACLK↓ to DOUT Enabled See Test Circuits ● 130 250 ns thCS Hold Time, CS After Last SCLK↓ (Note 6) 0 ns thDI Hold Time, DIN After SCLK↑ (Note 6) 50 ns thDO Time Output Data Remains Valid After SCLK↓ 50 ns tf DOUT Fall Time See Test Circuits ● 40 100 ns tr DOUT Rise Time See Test Circuits ● 40 100 ns tsuDI Setup Time, DIN Stable Before SCLK↑ (Note 6 and 9) 50 ns tsuCS Setup Time, CS↓ Before Clocking in (Note 6 and 9) 2 ACLK Cycles First Address Bit + 180ns tWHCS CS High Time During Conversion (Note 6) 52 ACLK Cycles CIN Input Capacitance Analog Inputs On Channel 100 pF Analog Inputs Off Channel 5 pF Digital Inputs 5 pF 1289fb 3
