Datasheet LTC1293, LTC1294, LTC1296 (Analog Devices) - 10

LTC1293/LTC1294/LTC1296
O U U W U APPLICATI S I FOR ATIO
The LTC 1293/4/6 is a data acquisition component which
INPUT DATA WORD
contains the following functional blocks: The LTC1293/4/6 seven-bit data word is clocked into the 1. 12-bit successive approximation capacitive A/D DIN input on the rising edge of the clock after chip select converter goes low and the start bit has been recognized. Further 2. Analog multiplexer (MUX) inputs on the DIN pin are then ignored until the next CS 3. Sample and hold (S/H) cycle. The input word is defined as follows: 4. Synchronous, half duplex serial interface UNIPOLAR/ POWER 5. Control and timing logic BIPOLAR SHUTDOWN START SGL/ ODD/ SELECT SELECT UNI MSBF DIFF PS SIGN 1 0
DIGITAL CONSIDERATIONS
MUX ADDRESS MSB FIRST/ LSB FIRST LTC1293 AI02
Serial Interface Start Bit
The LTC1293/4/6 communicates with microprocessors and other external circuitry via a synchronous, half duplex, The first "logical one" clocked into the DIN input after CS four-wire serial interface (see Operating Sequence). The goes low is the start bit. The start bit initiates the data clock (CLK) synchronizes the data transfer with each bit transfer and all leading zeroes which precede this logical being transmitted on the falling CLK edge and captured on one will be ignored. After the start bit is received the the rising CLK edge in both transmitting and receiving remaining bits of the input word will be clocked in. Further systems. The input data is first received and then the A/D inputs on the DIN pin are then ignored until the next CS conversion result is transmitted (half duplex). Because of cycle. CS DIN 1 DIN 2 D D OUT 1 OUT 2 SHIFT MUX 1 NULL SHIFT A/D CONVERSION ADDRESS IN BIT RESULT OUT LTC1293 AI01
MUX Address
the half duplex operation DIN and DOUT may be tied The four bits of the input word following the START BIT together allowing transmission over just 3 wired: CS, CLK assign the MUX configuration for the requested conver- and DATA (DIN/DOUT). Data transfer is initiated by a falling sion. For a given channel selection, the converter will chip select (CS) signal. After CS falls the LTC1293/4/6 measure the voltage between the two channels indicated looks for a start bit. After the start bit is received a 7-bit by the + and – signs in the selected row of the following input word is shifted into the DIN input which configures table. Note that in differential mode (SGL/DIFF = 0) mea- the LTC1293/4/6 and starts the conversion. After one null surements are limited to four adjacent input pairs with bit, the result of the conversion is output on the DOUT line. either polarity. In single ended mode, all input channels With the half duplex serial interface the DOUT data is from are measured with respect to COM. Only the +inputs have the current conversion. After the end of the data exchange sample and holds. Signals applied at the –inputs must not CS should be brought high. This resets the LTC1293/4/6 change more than the required accuracy during the con- in preparation for the next data exchange. version. 129346fs 10