Datasheet LTC1403, LTC1403A (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | Serial 14-Bit, 2.8Msps Sampling ADCs with Shutdown |
| Pages / Page | 22 / 9 — timing Diagram. LTC1403 Timing Diagram. LTC1403A Timing Diagram. Nap Mode … |
| File Format / Size | PDF / 370 Kb |
| Document Language | English |
timing Diagram. LTC1403 Timing Diagram. LTC1403A Timing Diagram. Nap Mode and Sleep Mode Waveforms. SCK to SDO Delay
Model Line for this Datasheet
Text Version of Document
LTC1403/LTC1403A
timing Diagram LTC1403 Timing Diagram
t2 t7 t3 t1 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 SCK t4 t5 CONV t6 tACQ INTERNAL S/H STATUS SAMPLE HOLD SAMPLE HOLD t8 t10 t8 t9 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION SDO Hi-Z Hi-Z D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X 1403A TD01 14-BIT DATA WORD tCONV tTHROUGHPUT *BITS MARKED "X" AFTER D0 SHOULD BE IGNORED.
LTC1403A Timing Diagram
t2 t7 t3 t1 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 SCK t4 t5 CONV t6 tACQ INTERNAL S/H STATUS SAMPLE HOLD SAMPLE HOLD t8 t10 t8 t9 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION SDO Hi-Z Hi-Z D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1403A TD01b 14-BIT DATA WORD tCONV tTHROUGHPUT
Nap Mode and Sleep Mode Waveforms
SLK t1 t1 CONV NAP SLEEP t12 V REF 1403A TD02 NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS
SCK to SDO Delay
SCK SCK VIH VIH t8 t10 t9 VOH 90% SDO SDO VOL 10% 1403A TD03 1403fc For more information www.linear.com/LTC1403 9 Document Outline Features Applications Block Diagram Description Absolute Maximum Ratings Order Information Pin Configuration Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram Applications Information Package Description Revision History Related Parts
timing Diagram LTC1403 Timing Diagram
t2 t7 t3 t1 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 SCK t4 t5 CONV t6 tACQ INTERNAL S/H STATUS SAMPLE HOLD SAMPLE HOLD t8 t10 t8 t9 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION SDO Hi-Z Hi-Z D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X 1403A TD01 14-BIT DATA WORD tCONV tTHROUGHPUT *BITS MARKED "X" AFTER D0 SHOULD BE IGNORED.
LTC1403A Timing Diagram
t2 t7 t3 t1 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 SCK t4 t5 CONV t6 tACQ INTERNAL S/H STATUS SAMPLE HOLD SAMPLE HOLD t8 t10 t8 t9 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION SDO Hi-Z Hi-Z D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1403A TD01b 14-BIT DATA WORD tCONV tTHROUGHPUT
Nap Mode and Sleep Mode Waveforms
SLK t1 t1 CONV NAP SLEEP t12 V REF 1403A TD02 NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS
SCK to SDO Delay
SCK SCK VIH VIH t8 t10 t9 VOH 90% SDO SDO VOL 10% 1403A TD03 1403fc For more information www.linear.com/LTC1403 9 Document Outline Features Applications Block Diagram Description Absolute Maximum Ratings Order Information Pin Configuration Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram Applications Information Package Description Revision History Related Parts
