Datasheet LTC1603 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | High Speed, 16-Bit, 250ksps Sampling A/D Converter with Shutdown |
| Pages / Page | 20 / 9 — APPLICATIONS INFORMATION. Figure 2a. Nap Mode to Sleep Mode Timing. … |
| File Format / Size | PDF / 261 Kb |
| Document Language | English |
APPLICATIONS INFORMATION. Figure 2a. Nap Mode to Sleep Mode Timing. Timing and Control
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LTC1603
U U W U APPLICATIONS INFORMATION
currents are shut down and only leakage current remains SHDN (about 1µA). Wake-up time from Sleep mode is much t3 slower since the reference circuit must power up and CS settle. Sleep mode wake-up time is dependent on the value 1603 F02a of the capacitor connected to the REFCOMP (Pin 4). The wake-up time is 160ms with the recommended 47µF
Figure 2a. Nap Mode to Sleep Mode Timing
capacitor. Shutdown is controlled by Pin 33 (SHDN). The ADC is in SHDN shutdown when SHDN is low. The shutdown mode is t4 selected with Pin 32 (CS). When SHDN is low, CS low selects nap and CS high selects sleep. CONVST 1603 F02b
Timing and Control Figure 2b. SHDN to CONVST Wake-Up Timing
Conversion start and data read operations are controlled by three digital inputs: CONVST, CS and RD. A falling edge applied to the CONVST pin will start a conversion after the CS ADC has been selected (i.e., CS is low). Once initiated, it cannot be restarted until the conversion is complete. t2 Converter status is indicated by the BUSY output. BUSY is CONVST low during a conversion. t1 We recommend using a narrow logic low or narrow logic RD high CONVST pulse to start a conversion as shown in 1603 F03 Figures 5 and 6. A narrow low or high CONVST pulse prevents the rising edge of the CONVST pulse from upset-
Figure 3. CS to CONVST Setup Timing
ting the critical bit decisions during the conversion time. Figure 4 shows the change of the differential nonlinearity error versus the low time of the CONVST pulse. As shown, 4 if CONVST returns high early in the conversion (e.g., CONVST low time <500ns), accuracy is unaffected. Simi- 3 larly, if CONVST returns high after the conversion is over (e.g., CONVST low time >tCONV), accuracy is unaffected. 2 For best results, keep t5 less than 500ns or greater than tCONV tACQ tCONV. CHANGE IN DNL (LSB) 1 Figures 5 through 9 show several different modes of operation. In modes 1a and 1b (Figures 5 and 6), CS and RD are both tied low. The falling edge of CONVST starts the 0 0 500 1000 1500 2000 2500 3000 3500 4000 conversion. The data outputs are always enabled and data CONVST LOW TIME, t5 (ns) 1603 F04 can be latched with the BUSY rising edge. Mode 1a shows
Figure 4. Change in DNL vs CONVST Low Time. Be Sure the
operation with a narrow logic low CONVST pulse. Mode 1b
CONVST Pulse Returns High Early in the Conversion or After
shows a narrow logic high CONVST pulse.
the End of Conversion
In mode 2 (Figure 7) CS is tied low. The falling edge of CONVST signal starts the conversion. Data outputs are in 1603f 9
U U W U APPLICATIONS INFORMATION
currents are shut down and only leakage current remains SHDN (about 1µA). Wake-up time from Sleep mode is much t3 slower since the reference circuit must power up and CS settle. Sleep mode wake-up time is dependent on the value 1603 F02a of the capacitor connected to the REFCOMP (Pin 4). The wake-up time is 160ms with the recommended 47µF
Figure 2a. Nap Mode to Sleep Mode Timing
capacitor. Shutdown is controlled by Pin 33 (SHDN). The ADC is in SHDN shutdown when SHDN is low. The shutdown mode is t4 selected with Pin 32 (CS). When SHDN is low, CS low selects nap and CS high selects sleep. CONVST 1603 F02b
Timing and Control Figure 2b. SHDN to CONVST Wake-Up Timing
Conversion start and data read operations are controlled by three digital inputs: CONVST, CS and RD. A falling edge applied to the CONVST pin will start a conversion after the CS ADC has been selected (i.e., CS is low). Once initiated, it cannot be restarted until the conversion is complete. t2 Converter status is indicated by the BUSY output. BUSY is CONVST low during a conversion. t1 We recommend using a narrow logic low or narrow logic RD high CONVST pulse to start a conversion as shown in 1603 F03 Figures 5 and 6. A narrow low or high CONVST pulse prevents the rising edge of the CONVST pulse from upset-
Figure 3. CS to CONVST Setup Timing
ting the critical bit decisions during the conversion time. Figure 4 shows the change of the differential nonlinearity error versus the low time of the CONVST pulse. As shown, 4 if CONVST returns high early in the conversion (e.g., CONVST low time <500ns), accuracy is unaffected. Simi- 3 larly, if CONVST returns high after the conversion is over (e.g., CONVST low time >tCONV), accuracy is unaffected. 2 For best results, keep t5 less than 500ns or greater than tCONV tACQ tCONV. CHANGE IN DNL (LSB) 1 Figures 5 through 9 show several different modes of operation. In modes 1a and 1b (Figures 5 and 6), CS and RD are both tied low. The falling edge of CONVST starts the 0 0 500 1000 1500 2000 2500 3000 3500 4000 conversion. The data outputs are always enabled and data CONVST LOW TIME, t5 (ns) 1603 F04 can be latched with the BUSY rising edge. Mode 1a shows
Figure 4. Change in DNL vs CONVST Low Time. Be Sure the
operation with a narrow logic low CONVST pulse. Mode 1b
CONVST Pulse Returns High Early in the Conversion or After
shows a narrow logic high CONVST pulse.
the End of Conversion
In mode 2 (Figure 7) CS is tied low. The falling edge of CONVST signal starts the conversion. Data outputs are in 1603f 9
