Datasheet LTC1608 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | High Speed, 16-Bit, 500ksps Sampling A/D Converter with Shutdown |
| Pages / Page | 20 / 4 — POWER REQUIRE E TS The. denotes specifications that apply over the full … |
| File Format / Size | PDF / 816 Kb |
| Document Language | English |
POWER REQUIRE E TS The. denotes specifications that apply over the full operating temperature range,
Model Line for this Datasheet
Text Version of Document
LTC1608
W U POWER REQUIRE E TS The
●
denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Positive Supply Voltage (Notes 12, 13) 4.75 5.25 V VSS Negative Supply Voltage (Note 12) – 4.75 – 5.25 V IDD Positive Supply Current CS = RD = 0V ● 22 35 mA Nap Mode CS = 0V, SHDN = 0V 1.5 2.4 mA Sleep Mode CS = 5V, SHDN = 0V 1 100 µA ISS Negative Supply Current CS = RD = 0V ● 32 49 mA Nap Mode CS = 0V, SHDN = 0V 1 100 µA Sleep Mode CS = 5V, SHDN = 0V 1 100 µA PD Power Dissipation CS = RD = 0V ● 270 420 mW Nap Mode CS = 0V, SHDN = 0V 7.5 12 mW Sleep Mode CS = 5V, SHDN = 0V 0.01 1 mW
W U TI I G CHARACTERISTICS The
●
denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL(MAX) Maximum Sampling Frequency ● 500 600 kHz tCONV Conversion Time ● 1.0 1.45 1.8 µs tACQ Acquisition Time (Notes 11, 14) ● 400 ns tACQ+CONV(MIN) Throughput Time (Acquisition + Conversion) ● 1.67 2 µs t1 CS to RD Setup Time (Notes 11, 12, 15) ● 0 ns t2 CS↓ to CONVST↓ Setup Time (Notes 11, 12) ● 10 ns t3 SHDN↓ to CS↑ Setup Time (Notes 11, 12) ● 10 ns t4 SHDN↑ to CONVST↓ Wake-Up Time CS = Low (Note 12) 400 ns t5 CONVST Low Time (Note 12) ● 40 ns t6 CONVST to BUSY Delay CL = 25pF 36 ns ● 80 ns t7 Data Ready Before BUSY↑ 60 ns ● 32 ns t8 Delay Between Conversions (Note 12) ● 200 ns t9 Wait Time RD↓ After BUSY↑ (Note 12) ● – 5 ns t10 Data Access Time After RD↓ CL = 25pF 25 40 ns ● 50 ns CL = 100pF (Note 11) 45 60 ns ● 75 ns t11 Bus Relinquish Time 30 50 ns ● 60 ns t12 RD Low Time (Note 12) ● t10 ns t13 CONVST High Time (Note 12) ● 40 ns t14 Aperture Delay of Sample-and-Hold 2 ns
Note 1:
Absolute Maximum Ratings are those values beyond which the life
Note 3:
When these pin voltages are taken below VSS or above VDD, they of a device may be impaired. will be clamped by internal diodes. This product can handle input currents
Note 2:
All voltage values are with respect to ground with DGND, OGND greater than 100mA below VSS or above VDD without latchup. and AGND wired together unless otherwise noted. 4
W U POWER REQUIRE E TS The
●
denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Positive Supply Voltage (Notes 12, 13) 4.75 5.25 V VSS Negative Supply Voltage (Note 12) – 4.75 – 5.25 V IDD Positive Supply Current CS = RD = 0V ● 22 35 mA Nap Mode CS = 0V, SHDN = 0V 1.5 2.4 mA Sleep Mode CS = 5V, SHDN = 0V 1 100 µA ISS Negative Supply Current CS = RD = 0V ● 32 49 mA Nap Mode CS = 0V, SHDN = 0V 1 100 µA Sleep Mode CS = 5V, SHDN = 0V 1 100 µA PD Power Dissipation CS = RD = 0V ● 270 420 mW Nap Mode CS = 0V, SHDN = 0V 7.5 12 mW Sleep Mode CS = 5V, SHDN = 0V 0.01 1 mW
W U TI I G CHARACTERISTICS The
●
denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL(MAX) Maximum Sampling Frequency ● 500 600 kHz tCONV Conversion Time ● 1.0 1.45 1.8 µs tACQ Acquisition Time (Notes 11, 14) ● 400 ns tACQ+CONV(MIN) Throughput Time (Acquisition + Conversion) ● 1.67 2 µs t1 CS to RD Setup Time (Notes 11, 12, 15) ● 0 ns t2 CS↓ to CONVST↓ Setup Time (Notes 11, 12) ● 10 ns t3 SHDN↓ to CS↑ Setup Time (Notes 11, 12) ● 10 ns t4 SHDN↑ to CONVST↓ Wake-Up Time CS = Low (Note 12) 400 ns t5 CONVST Low Time (Note 12) ● 40 ns t6 CONVST to BUSY Delay CL = 25pF 36 ns ● 80 ns t7 Data Ready Before BUSY↑ 60 ns ● 32 ns t8 Delay Between Conversions (Note 12) ● 200 ns t9 Wait Time RD↓ After BUSY↑ (Note 12) ● – 5 ns t10 Data Access Time After RD↓ CL = 25pF 25 40 ns ● 50 ns CL = 100pF (Note 11) 45 60 ns ● 75 ns t11 Bus Relinquish Time 30 50 ns ● 60 ns t12 RD Low Time (Note 12) ● t10 ns t13 CONVST High Time (Note 12) ● 40 ns t14 Aperture Delay of Sample-and-Hold 2 ns
Note 1:
Absolute Maximum Ratings are those values beyond which the life
Note 3:
When these pin voltages are taken below VSS or above VDD, they of a device may be impaired. will be clamped by internal diodes. This product can handle input currents
Note 2:
All voltage values are with respect to ground with DGND, OGND greater than 100mA below VSS or above VDD without latchup. and AGND wired together unless otherwise noted. 4
