LTC1750 UUDIGITAL I PUTS A D DIGITAL OUTPUTS The ● indicates specifications which apply over the fulloperating temperature range, otherwise specifications are at TA = 25 ° C. (Note 5)SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS VIH High Level Input Voltage VDD = 5.25V, MSBINV and PGA ● 2.4 V VIL Low Level Input Voltage VDD = 4.75V, MSBINV and PGA ● 0.8 V IIN Digital Input Current VIN = 0V to VDD ● ±10 µA CIN Digital Input Capacitance MSBINV and PGA Only 1.5 pF VOH High Level Output Voltage OVDD = 4.75V IO = –10µA 4.74 V IO = – 200µA ● 4 4.74 V VOL Low Level Output Voltage OVDD = 4.75V IO = 160µA 0.05 V IO = 1.6mA ● 0.1 0.4 V ISOURCE Output Source Current VOUT = 0V – 50 mA ISINK Output Sink Current VOUT = 5V 50 mA WUPOWER REQUIRE E TS The ● indicates specifications which apply over the full operating temperaturerange, otherwise specifications are at TA = 25 ° C. (Note 5)SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS VDD Positive Supply Voltage 4.75 5.25 V IDD Positive Supply Current ● 290 338 mA PDIS Power Dissipation ● 1.45 1.69 W OVDD Digital Output Supply Voltage 0.5 VDD V W UTI I G CHARACTERISTICS The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25 ° C. (Note 5)SYMBOLPARAMETERCONDITIONSMINTYPMAXUNITS t0 ENC Period (Note 9) ● 12.5 2000 ns t1 ENC High (Note 8) ● 6 1000 ns t2 ENC Low (Note 8) ● 6 1000 ns t3 Aperture Delay (Note 8) 0 ns t4 ENC to CLKOUT Falling CL = 10pF (Note 8) ● 1 2.4 4 ns t5 ENC to CLKOUT Rising CL = 10pF (Note 8) t1 + t4 ns For 80Msps 50% Duty Cycle CL = 10pF (Note 8) ● 7.25 8.65 10.25 ns t6 ENC to DATA Delay CL = 10pF (Note 8) ● 2 4.9 7.2 ns t7 ENC to DATA Delay (Hold Time) (Note 8) ● 1.4 3.4 4.7 ns t8 ENC to DATA Delay (Setup Time) CL = 10pF (Note 8) t0 – t6 ns For 80Msps 50% Duty Cycle CL = 10pF (Note 8) ● 5.3 7.6 10.5 ns t9 CLKOUT to DATA Delay (Hold Time), (Note 8) ● 6 ns 80Msps 50% Duty Cycle t10 CLKOUT to DATA Delay (Setup Time), CL = 10pF (Note 8) ● 2.1 ns 80Msps 50% Duty Cycle Data Latency 5 cycles 1750f 4