Datasheet LTC2122 (Analog Devices) - 10

LTC2122
PIN FUNCTIONS VDD (Pins 1, 12, 13, 23, 24, 37, 38, 48):
1.8V Power the SYNC~ signal causes the LTC2122 to output K28.5 Supply. Bypass to ground with 0.1µF ceramic capacitors. commas (SYNC~ = SYNC~+ – SYNC~–). Adjacent pins can share bypass capacitor. In subclass 2 a low to high transition of SYNC~ is sampled
GND (Pins 2, 8, 11, 14, 17, 20, 39, 40, 47, Exposed Pad
on the rising edge of DEVCLK to reset the internal dividers
Pin 49):
Device Power Ground. The exposed pad must be and set up deterministic latency. soldered to the PCB ground.
OVDD (Pins 25, 26, 35, 36):
1.2V to 1.9V Output Driver Supply.
A + – INA /AINA (Pins 3, 4):
Analog Input Pair for Channel A. Bypass each pair to ground with 0.1μF ceramic capacitors.
SENSE (Pin 5):
Reference Programming Pin. Connecting
CMLOUT_B0–/CMLOUT_B0+ (Pins 29, 30):
Current Mode SENSE to VDD selects the internal reference and a ±0.75V Logic Output Pair for Channel B in two lane mode. Must input range. An external reference between 1.2V and 1.3V be terminated with a 50Ω resistor to OVDD, a differential applied to SENSE selects an input range of ±0.6 × VSENSE. 100Ω resistor to the complementary output, or AC coupled
V
to another termination voltage.
REF (Pin 6):
Reference Voltage Output. Bypass to ground with a 2.2μF ceramic capacitor. Nominally 1.25V.
CMLOUT_A0–/CMLOUT_A0+ (Pins 31, 32):
Current Mode
V
Logic Output Pair for Channel A in two lane mode or for
CM (Pin 7):
Common Mode Bias Output. Nominally equal to 0.435 • V both Channel A and Channel B in one lane mode. Must DD. VCM should be used to bias the common mode of the analog inputs. Bypass to ground with a 0.1μF be terminated with a 50Ω resistor to OVDD, a differential ceramic capacitor. 100Ω resistor to the complementary output, or AC coupled to another termination voltage.
A – + INB /AINB (Pins 9, 10):
Analog Input Pair for Channel B.
OF–/OF+ (Pins 41, 42):
Over/Underflow LVDS Digital
DEVCLK–/DEVCLK+ (Pins 15, 16):
Device Clock Input Pair. Output. OF is high when an overflow or underflow has The sample clock is derived from this differential signal. occurred. The overflows for channel A and channel B are An internal DEVCLK divider may be programmed through multiplexed together and transmitted at twice the sample the SPI to either divide by one or two (DEVCLK = DEV- frequency (OF = OF+ – OF–). CLK+ – DEVCLK–).
SDO (Pin 43):
Serial Interface Data Output. SDO is the In divide-by-one mode, the analog signal is sampled on optional serial interface data output. Data on SDO is read the falling edge of DEVCLK. back from the mode control registers and can be latched on the falling edge of SCK. SDO is an open-drain N-channel In divide-by-two mode, the analog signal is sampled once MOSFET output that requires an external 2k pull-up resis- every two DEVCLK cycles on the rising edge of DEVCLK. tor from 1.8V to 3.3V. If readback from the mode control The actual sampling cycle is established at the time of the registers is not needed, the pull-up resistor is not neces- clock divider initialization. In subclass 1, a low-to-high tran- sary and SDO can be left unconnected. sition of the SYSREF signal will initialize the divide-by-two circuit on the first rising edge of DEVCLK. In subclass 2, a
SDI (Pin 44):
Serial Interface Data Input. SDI is the serial low to high transition of the SYNC~ signal will initialize the interface data input. Data on SDI is clocked into the mode control registers on the rising edge of SCK. SDI can be divide-by-two circuit on the first rising edge of DEVCLK. driven with 1.8V to 3.3V logic.
SYSREF+/SYSREF– (Pins 18, 19):
A JESD204B Subclass
SCK (Pin 45):
Serial Interface Clock Input. SCK is the 1 Input Signal Pair. A low to high transition of SYSREF is serial interface clock input. SCK can be driven with 1.8V sampled on the rising edge of DEVCLK to reset the inter- to 3.3V logic. nal dividers and set up deterministic latency (SYSREF = SYSREF+ – SYSREF–).
CS (Pin 46):
Serial Interface Chip Select Input. When CS is low, SCK is enabled for shifting data on SDI into the
SYNC~+/SYNC~– (Pins 21, 22):
A JESD204B Synchroniza- mode control registers. SCK must be low at the time of tion Input Signal Pair. Used to establish initial Code-Group the falling edge of CS, for proper operation. CS can be synchronization for all three subclasses. A low level of driven with 1.8V to 3.3V logic. 2122fb 10 For more information www.linear.com/LTC2122 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Power Requirements Digital Inputs And Outputs Digital Inputs And Outputs Timing characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram SPI Timing Definitions ADC PERFORMANCE TERMS SERIAL INTERFACE TERMS Applications Information CONVERTER OPERATION INPUT DRIVE CIRCUITS GROUNDING AND BYPASSING HEAT TRANSFER Typical Applications Package Description Revision History Typical Application Related Parts