Datasheet LTC2122 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | Dual14-Bit 170Msps ADC with JESD204B Serial Outputs |
| Pages / Page | 50 / 1 — FEATURES. DESCRIPTION. 6.0Gbps JESD204B Interface. APPLICATIONS. TYPICAL … |
| File Format / Size | PDF / 1.5 Mb |
| Document Language | English |
FEATURES. DESCRIPTION. 6.0Gbps JESD204B Interface. APPLICATIONS. TYPICAL APPLICATION. 64k Point 2-Tone FFT,. IN = 71MHz and 69MHz,
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LTC2122 Dual 14-Bit 170Msps ADC with JESD204B Serial Outputs
FEATURES DESCRIPTION
n
6.0Gbps JESD204B Interface
The LTC®2122 is a 2-channel simultaneous sampling n Only One Output Lane Required for Both ADCs 170Msps 14-bit A/D converter with serial JESD204B (FS ≤ 150Msps) outputs. It is designed for digitizing high frequency, n 70dBFS SNR wide dynamic range signals. It is perfect for demanding n 90dBFS SFDR communications applications with AC performance that n Low Power: 751mW Total includes 70dBFS SNR and 90dBFS spurious free dynamic n Single 1.8V Supply range (SFDR). The 1.25GHz input bandwidth allows the n Easy to Drive 1.5VP-P Input Range ADC to under-sample high frequencies. n 1.25GHz Full Power Bandwidth S/H The JESD204B serial interface simplifies the PCB design by n Optional Clock Divide by Two minimizing the number of data lines required. At 170Msps, n Optional Clock Duty Cycle Stabilizer only two 3.4Gbps output lanes are required. For sample n Low Power Sleep and Nap Modes rates up to 150Msps, both ADCs may share the same n Serial SPI Port for Configuration output lane at up to 6.0Gbps. n 48-Lead (7mm × 7mm) QFN Package The DEVCLK+ and DEVCLK– inputs can be driven differen-
APPLICATIONS
tially with sine wave, PECL, or LVDS signals. An optional n clock divide-by-two circuit or clock duty cycle stabilizer Communications n maintains high performance at full speed for a wide range Cellular Base Stations n of clock duty cycles. Software Defined Radios L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear n Medical Imaging Technology Corporation. All other trademarks are the property of their respective owners. n High Definition Video n Test and Measurement Instrumentation
TYPICAL APPLICATION
OVDD
64k Point 2-Tone FFT,
1.2V TO 1.9V
f
LTC2122
IN = 71MHz and 69MHz,
50Ω 50Ω
–7dBFS, 170Msps
0 ANALOG JESD204B 14-BIT ADC SERIALIZER 3.4Gbps INPUT LOGIC –20 –40 CLOCK JESD204B –60 CLOCK PLL ÷ 2 OR ÷ 1 OVDD FPGA OR ASIC 1.2V TO 1.9V –80 AMPLITUDE (dBFS) (170MHz OR 340MHz) 50Ω 50Ω –100 ANALOG JESD204B –120 14-BIT ADC SERIALIZER 3.4Gbps INPUT LOGIC 0 10 20 30 40 50 60 70 80 FREQUENCY (MHz) 2122 TA01a 2122 TA01 2122fb For more information www.linear.com/LTC2122 1 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Power Requirements Digital Inputs And Outputs Digital Inputs And Outputs Timing characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram SPI Timing Definitions ADC PERFORMANCE TERMS SERIAL INTERFACE TERMS Applications Information CONVERTER OPERATION INPUT DRIVE CIRCUITS GROUNDING AND BYPASSING HEAT TRANSFER Typical Applications Package Description Revision History Typical Application Related Parts
FEATURES DESCRIPTION
n
6.0Gbps JESD204B Interface
The LTC®2122 is a 2-channel simultaneous sampling n Only One Output Lane Required for Both ADCs 170Msps 14-bit A/D converter with serial JESD204B (FS ≤ 150Msps) outputs. It is designed for digitizing high frequency, n 70dBFS SNR wide dynamic range signals. It is perfect for demanding n 90dBFS SFDR communications applications with AC performance that n Low Power: 751mW Total includes 70dBFS SNR and 90dBFS spurious free dynamic n Single 1.8V Supply range (SFDR). The 1.25GHz input bandwidth allows the n Easy to Drive 1.5VP-P Input Range ADC to under-sample high frequencies. n 1.25GHz Full Power Bandwidth S/H The JESD204B serial interface simplifies the PCB design by n Optional Clock Divide by Two minimizing the number of data lines required. At 170Msps, n Optional Clock Duty Cycle Stabilizer only two 3.4Gbps output lanes are required. For sample n Low Power Sleep and Nap Modes rates up to 150Msps, both ADCs may share the same n Serial SPI Port for Configuration output lane at up to 6.0Gbps. n 48-Lead (7mm × 7mm) QFN Package The DEVCLK+ and DEVCLK– inputs can be driven differen-
APPLICATIONS
tially with sine wave, PECL, or LVDS signals. An optional n clock divide-by-two circuit or clock duty cycle stabilizer Communications n maintains high performance at full speed for a wide range Cellular Base Stations n of clock duty cycles. Software Defined Radios L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear n Medical Imaging Technology Corporation. All other trademarks are the property of their respective owners. n High Definition Video n Test and Measurement Instrumentation
TYPICAL APPLICATION
OVDD
64k Point 2-Tone FFT,
1.2V TO 1.9V
f
LTC2122
IN = 71MHz and 69MHz,
50Ω 50Ω
–7dBFS, 170Msps
0 ANALOG JESD204B 14-BIT ADC SERIALIZER 3.4Gbps INPUT LOGIC –20 –40 CLOCK JESD204B –60 CLOCK PLL ÷ 2 OR ÷ 1 OVDD FPGA OR ASIC 1.2V TO 1.9V –80 AMPLITUDE (dBFS) (170MHz OR 340MHz) 50Ω 50Ω –100 ANALOG JESD204B –120 14-BIT ADC SERIALIZER 3.4Gbps INPUT LOGIC 0 10 20 30 40 50 60 70 80 FREQUENCY (MHz) 2122 TA01a 2122 TA01 2122fb For more information www.linear.com/LTC2122 1 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Power Requirements Digital Inputs And Outputs Digital Inputs And Outputs Timing characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram SPI Timing Definitions ADC PERFORMANCE TERMS SERIAL INTERFACE TERMS Applications Information CONVERTER OPERATION INPUT DRIVE CIRCUITS GROUNDING AND BYPASSING HEAT TRANSFER Typical Applications Package Description Revision History Typical Application Related Parts
