Datasheet LTC2175-12, LTC2174-12, LTC2173-12 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 12-Bit, 125Msps Low Power Quad ADCs |
| Pages / Page | 34 / 8 — TiMing DiagraMs. 2-Lane Output Mode, 16-Bit Serialization. 2-Lane Output … |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
TiMing DiagraMs. 2-Lane Output Mode, 16-Bit Serialization. 2-Lane Output Mode, 14-Bit Serialization
Model Line for this Datasheet
- LTC2173CUKG-12#PBF LTC2173CUKG-12#PBF LTC2173CUKG-12#TRPBF LTC2173CUKG-12#TRPBF LTC2173IUKG-12#PBF LTC2173IUKG-12#PBF LTC2173IUKG-12#TRPBF LTC2173IUKG-12#TRPBF
Text Version of Document
LTC2175-12/ LTC2174-12/LTC2173-12
TiMing DiagraMs 2-Lane Output Mode, 16-Bit Serialization
tAP N+1 ANALOG N INPUT tENCH tENCL ENC– ENC+ t DCO– SER DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D3 D1 DX* 0 D11 D9 D7 D5 D3 D1 DX* 0 D11 D9 D7 OUT#A+ OUT#B– D2 D0 DY* 0 D10 D8 D6 D4 D2 D0 DY* 0 D10 D8 D6 OUT#B+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 217512 TD01 *DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.
2-Lane Output Mode, 14-Bit Serialization
tAP ANALOG N+2 N INPUT t N+1 ENCH tENCL ENC– ENC+ t DCO– SER DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D5 D3 D1 DX* D11 D9 D7 D5 D3 D1 DX* D11 D9 D7 D5 D3 D1 DX* D11 D9 D7 OUT#A+ OUT#B– D4 D2 D0 DY* D10 D8 D6 D4 D2 D0 DY* D10 D8 D6 D4 D2 D0 DY* D10 D8 D6 OUT#B+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 SAMPLE N-3 217512 TD02 NOTE THAT IN THIS MODE FR+/FR– HAS TWO TIMES THE PERIOD OF ENC+/ENC– *DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS. 21754312fa 8 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
TiMing DiagraMs 2-Lane Output Mode, 16-Bit Serialization
tAP N+1 ANALOG N INPUT tENCH tENCL ENC– ENC+ t DCO– SER DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D3 D1 DX* 0 D11 D9 D7 D5 D3 D1 DX* 0 D11 D9 D7 OUT#A+ OUT#B– D2 D0 DY* 0 D10 D8 D6 D4 D2 D0 DY* 0 D10 D8 D6 OUT#B+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 217512 TD01 *DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.
2-Lane Output Mode, 14-Bit Serialization
tAP ANALOG N+2 N INPUT t N+1 ENCH tENCL ENC– ENC+ t DCO– SER DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D5 D3 D1 DX* D11 D9 D7 D5 D3 D1 DX* D11 D9 D7 D5 D3 D1 DX* D11 D9 D7 OUT#A+ OUT#B– D4 D2 D0 DY* D10 D8 D6 D4 D2 D0 DY* D10 D8 D6 D4 D2 D0 DY* D10 D8 D6 OUT#B+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 SAMPLE N-3 217512 TD02 NOTE THAT IN THIS MODE FR+/FR– HAS TWO TIMES THE PERIOD OF ENC+/ENC– *DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS. 21754312fa 8 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
