Datasheet LTC2175-12, LTC2174-12, LTC2173-12 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 12-Bit, 125Msps Low Power Quad ADCs |
| Pages / Page | 34 / 10 — TiMing DiagraMs. One-Lane Output Mode, 14-Bit Serialization. One-Lane … |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
TiMing DiagraMs. One-Lane Output Mode, 14-Bit Serialization. One-Lane Output Mode, 12-Bit Serialization
Model Line for this Datasheet
- LTC2173CUKG-12#PBF LTC2173CUKG-12#PBF LTC2173CUKG-12#TRPBF LTC2173CUKG-12#TRPBF LTC2173IUKG-12#PBF LTC2173IUKG-12#PBF LTC2173IUKG-12#TRPBF LTC2173IUKG-12#TRPBF
Text Version of Document
LTC2175-12/ LTC2174-12/LTC2173-12
TiMing DiagraMs One-Lane Output Mode, 14-Bit Serialization
tAP ANALOG N+1 N INPUT tENCH tENCL ENC– ENC+ t DCO– SER DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D1 D0 DX* DY* D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DX* DY* D11 D10 D9 D8 OUT#A+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 217512 TD06 OUT#B+, OUT#B– ARE DISABLED *DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.
One-Lane Output Mode, 12-Bit Serialization
tAP ANALOG N+1 N INPUT tENCH tENCL ENC– ENC+ t DCO– SER DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 OUT#A+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 217512 TD07 OUT#B+, OUT#B– ARE DISABLED
SPI Port Timing (Readback Mode)
tS tDS tDH tSCK tH CS SCK tDO SDI R/W A6 A5 A4 A3 A2 A1 A0 XX XX XX XX XX XX XX XX SDO D7 D6 D5 D4 D3 D2 D1 D0 HIGH IMPEDANCE
SPI Port Timing (Write Mode)
CS SCK SDI R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SDO 217512 TD04 HIGH IMPEDANCE 21754312fa 10 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
TiMing DiagraMs One-Lane Output Mode, 14-Bit Serialization
tAP ANALOG N+1 N INPUT tENCH tENCL ENC– ENC+ t DCO– SER DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D1 D0 DX* DY* D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DX* DY* D11 D10 D9 D8 OUT#A+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 217512 TD06 OUT#B+, OUT#B– ARE DISABLED *DX AND DY ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION DX AND DY ARE SET TO LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.
One-Lane Output Mode, 12-Bit Serialization
tAP ANALOG N+1 N INPUT tENCH tENCL ENC– ENC+ t DCO– SER DCO+ tFRAME tDATA tSER FR– FR+ tPD tSER OUT#A– D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 OUT#A+ SAMPLE N-6 SAMPLE N-5 SAMPLE N-4 217512 TD07 OUT#B+, OUT#B– ARE DISABLED
SPI Port Timing (Readback Mode)
tS tDS tDH tSCK tH CS SCK tDO SDI R/W A6 A5 A4 A3 A2 A1 A0 XX XX XX XX XX XX XX XX SDO D7 D6 D5 D4 D3 D2 D1 D0 HIGH IMPEDANCE
SPI Port Timing (Write Mode)
CS SCK SDI R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SDO 217512 TD04 HIGH IMPEDANCE 21754312fa 10 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts
