Datasheet LTC2209 (Analog Devices)

LTC2209 16-Bit, 160Msps ADC
Features Description
n
Sample Rate: 160Msps
The LTC®2209 is a 160Msps 16-bit A/D converter designed n
77.3dBFS Noise Floor
for digitizing high frequency, wide dynamic range signals n
100dB SFDR
with input frequencies up to 700MHz. The input range of n
SFDR >84dB at 250MHz (1.5VP-P Input Range)
the ADC can be optimized with the PGA front end. n
PGA Front End (2.25VP-P or 1.5VP-P Input Range)
The LTC2209 is perfect for demanding communications n
700MHz Full Power Bandwidth S/H
applications, with AC performance that includes 77.3dBFS n
Optional Internal Dither
Noise Floor and 100dB spurious free dynamic range n
Optional Data Output Randomizer
(SFDR). Ultra low jitter of 70fsRMS allows undersampling n LVDS or CMOS Outputs of high input frequencies with excellent noise performance. n Single 3.3V Supply Maximum DC specs include ±5.5LSB INL, ±1LSB DNL (no n Power Dissipation: 1.53W missing codes). n Clock Duty Cycle Stabilizer n Pin-Compatible Family: The digital output can be either differential LVDS or 130Msps: LTC2208 (16-Bit), LTC2208-14 (14-Bit) single-ended CMOS. There are two format options for 105Msps: LTC2217 (16-Bit) the CMOS outputs: a single bus running at the full data n 64-Pin (9mm × 9mm) QFN Package rate or demultiplexed busses running at half data rate. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V.
applications
The ENC+ and ENC– inputs may be driven differentially n Telecommunications or single-ended with a sine wave, PECL, LVDS, TTL or n Receivers CMOS inputs. An optional clock duty cycle stabilizer al- n Cellular Base Stations lows high performance at full speed with a wide range of n Spectrum Analysis clock duty cycles. n Imaging Systems L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. n ATE All other trademarks are the property of their respective owners.
typical application
3.3V SENSE
64k Point FFT, fIN = 15.1MHz, –1dBFS, PGA = 0
OV V 1.25V INTERNAL ADC DD CM 0.5V TO 3.6V COMMON MODE REFERENCE 0 2.2µF BIAS VOLTAGE GENERATOR 1µF –10 –20 OF –30 A + IN + CLKOUT –40 16-BIT CORRECTION OUTPUT ANALOG CMOS S/H D15 –50 PIPELINED LOGIC AND DRIVERS INPUT OR AMP • ADC CORE –60 – – SHIFT REGISTER • LVDS A • –70 IN D0 –80 AMPLITUDE (dBFS) –90 OGND –100 CLOCK/DUTY –110 CYCLE V 3.3V DD –120 CONTROL 1µF 1µF 1µF GND –130 0 10 20 30 40 50 60 70 80 2209 TA01 FREQUENCY (MHz) ENC + ENC – PGA SHDN DITH MODE LVDS RAND 2209 TA01b ADC CONTROL INPUTS 2209fb 1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Common Mode Bias Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Electrical Characteristics Timing Diagram Typical Performance Characteristics Pin Functions Block Diagram Definitions Applications Information Package Description Revision History Related Parts