Datasheet LTC2224 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 12-Bit, 135Msps ADC |
| Pages / Page | 24 / 5 — POWER REQUIRE E TS The. denotes the specifications which apply over the … |
| File Format / Size | PDF / 625 Kb |
| Document Language | English |
POWER REQUIRE E TS The. denotes the specifications which apply over the full operating temperature
Model Line for this Datasheet
Text Version of Document
LTC2224
W U POWER REQUIRE E TS The
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 8) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Analog Supply Voltage ● 3.1 3.3 3.5 V OVDD Output Supply Voltage ● 0.5 3.3 3.6 V IVDD Analog Supply Current ● 191 206 mA PDISS Power Dissipation ● 630 680 mW PSHDN Shutdown Power SHDN = High, OE = High, No CLK 2 mW PNAP Nap Mode Power SHDN = High, OE = Low, No CLK 35 mW
W U TI I G CHARACTERISTICS The
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency ● 1 135 MHz tL ENC Low Time Duty Cycle Stabilizer Off ● 3.5 3.7 500 ns Duty Cycle Stabilizer On ● 2 3.7 500 ns tH ENC High Time Duty Cycle Stabilizer Off ● 3.5 3.7 500 ns Duty Cycle Stabilizer On ● 2 3.7 500 ns tAP Sample-and-Hold Aperture Delay 0 ns tOE Output Enable Delay (Note 7) ● 5 10 ns tD ENC to DATA Delay (Note 7) ● 1.3 2.1 3.5 ns tC ENC to CLOCKOUT Delay (Note 7) ● 1.3 2.1 3.5 ns DATA to CLOCKOUT Skew (tC - tD) (Note 7) ● –0.6 0 0.6 ns Pipeline Latency 5 Cycles
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 5:
Integral nonlinearity is defined as the deviation of a code from a “best may cause permanent damage to the device. Exposure to any Absolute straight line” fit to the transfer curve. The deviation is measured from the Maximum Rating condition for extended periods may affect device center of the quantization band. reliability and lifetime.
Note 6:
Offset error is the offset voltage measured from –0.5 LSB when the
Note 2:
All voltage values are with respect to ground with GND and OGND output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2’s wired together (unless otherwise noted). complement output mode.
Note 3:
When these pin voltages are taken below GND or above VDD, they will
Note 7:
Guaranteed by design, not subject to test. be clamped by internal diodes. This product can handle input currents of
Note 8:
VDD = 3.3V, OVDD = 1.8V, fSAMPLE = 135MHz, differential greater than 100mA below GND or above VDD without latchup. ENC+/ENC– = 2VP-P sine wave, input range = 1VP-P with differential drive,
Note 4:
VDD = 3.3V, OVDD = 1.8V, fSAMPLE = 135MHz, differential output CLOAD = 5pF. ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted. 2224fa 5
W U POWER REQUIRE E TS The
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 8) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Analog Supply Voltage ● 3.1 3.3 3.5 V OVDD Output Supply Voltage ● 0.5 3.3 3.6 V IVDD Analog Supply Current ● 191 206 mA PDISS Power Dissipation ● 630 680 mW PSHDN Shutdown Power SHDN = High, OE = High, No CLK 2 mW PNAP Nap Mode Power SHDN = High, OE = Low, No CLK 35 mW
W U TI I G CHARACTERISTICS The
●
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency ● 1 135 MHz tL ENC Low Time Duty Cycle Stabilizer Off ● 3.5 3.7 500 ns Duty Cycle Stabilizer On ● 2 3.7 500 ns tH ENC High Time Duty Cycle Stabilizer Off ● 3.5 3.7 500 ns Duty Cycle Stabilizer On ● 2 3.7 500 ns tAP Sample-and-Hold Aperture Delay 0 ns tOE Output Enable Delay (Note 7) ● 5 10 ns tD ENC to DATA Delay (Note 7) ● 1.3 2.1 3.5 ns tC ENC to CLOCKOUT Delay (Note 7) ● 1.3 2.1 3.5 ns DATA to CLOCKOUT Skew (tC - tD) (Note 7) ● –0.6 0 0.6 ns Pipeline Latency 5 Cycles
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 5:
Integral nonlinearity is defined as the deviation of a code from a “best may cause permanent damage to the device. Exposure to any Absolute straight line” fit to the transfer curve. The deviation is measured from the Maximum Rating condition for extended periods may affect device center of the quantization band. reliability and lifetime.
Note 6:
Offset error is the offset voltage measured from –0.5 LSB when the
Note 2:
All voltage values are with respect to ground with GND and OGND output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2’s wired together (unless otherwise noted). complement output mode.
Note 3:
When these pin voltages are taken below GND or above VDD, they will
Note 7:
Guaranteed by design, not subject to test. be clamped by internal diodes. This product can handle input currents of
Note 8:
VDD = 3.3V, OVDD = 1.8V, fSAMPLE = 135MHz, differential greater than 100mA below GND or above VDD without latchup. ENC+/ENC– = 2VP-P sine wave, input range = 1VP-P with differential drive,
Note 4:
VDD = 3.3V, OVDD = 1.8V, fSAMPLE = 135MHz, differential output CLOAD = 5pF. ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted. 2224fa 5
