Datasheet LTC2226H (Analog Devices) - 4

LTC2226H
DIGITAL INPUTS AND DIGITAL OUTPUTS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS LOGIC OUTPUTS OVDD = 3V
COZ Hi-Z Output Capacitance OE = High (Note 7) 3 pF ISOURCE Output Source Current VOUT = 0V 50 mA ISINK Output Sink Current VOUT = 3V 50 mA VOH High Level Output Voltage IO = –10µA 2.995 V IO = –200µA l 2.7 2.99 V VOL Low Level Output Voltage IO = 10µA 0.005 V IO = 1.6mA l 0.09 0.4 V
OVDD = 2.5V
VOH High Level Output Voltage IO = –200µA 2.49 V VOL Low Level Output Voltage IO = 1.6mA 0.09 V
OVDD = 1.8V
VOH High Level Output Voltage IO = –200µA 1.79 V VOL Low Level Output Voltage IO = 1.6mA 0.09 V
POWER REQUIREMENTS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 8) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Analog Supply Voltage (Note 9) l 2.8 3 3.5 V OVDD Output Supply Voltage (Note 9) l 0.5 3 3.6 V IVDD Supply Current l 25 30 mA PDISS Power Dissipation l 75 90 mW PSHDN Shutdown Power SHDN = H, OE = H, No CLK 2 mW PNAP Nap Mode Power SHDN = H, OE = L, No CLK 15 mW
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 9) l 1 25 MHz tL CLK Low Time Duty Cycle Stabilizer Off l 18.9 20 500 ns Duty Cycle Stabilizer On l 5 20 500 ns (Note 7) tH CLK High Time Duty Cycle Stabilizer Off l 18.9 20 500 ns Duty Cycle Stabilizer On l 5 20 500 ns (Note 7) tAP Sample-and-Hold Aperture Delay 0 ns tD CLK to DATA Delay CL = 5pF (Note 7) l 1.4 2.7 6 ns Data Access Time After OE↓ CL = 5pF (Note 7) l 4.3 12 ns BUS Relinquish Time (Note 7) l 3.3 10 ns Pipeline Latency 5 Cycles 2226hfc 4