Datasheet LTC2229 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 12-Bit, 80Msps Low Power 3V ADC |
| Pages / Page | 24 / 8 — PI FU CTIO S. AIN+ (Pin 1):. NC (Pins 12, 13):. AIN- (Pin 2):. D0–D11 … |
| File Format / Size | PDF / 566 Kb |
| Document Language | English |
PI FU CTIO S. AIN+ (Pin 1):. NC (Pins 12, 13):. AIN- (Pin 2):. D0–D11 (Pins 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26,
Model Line for this Datasheet
Text Version of Document
LTC2229
U U U PI FU CTIO S AIN+ (Pin 1):
Positive Differential Analog Input.
NC (Pins 12, 13):
Do Not Connect These Pins.
AIN- (Pin 2):
Negative Differential Analog Input.
D0–D11 (Pins 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26, REFH (Pins 3, 4):
ADC High Reference. Short together and
27):
Digital Outputs. D11 is the MSB. bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as
OGND (Pin 20):
Output Driver Ground. close to the pin as possible. Also bypass to pins 5, 6 with an additional 2.2µF ceramic chip capacitor and to ground
OVDD (Pin 21):
Positive Supply for the Output Drivers. with a 1µF ceramic chip capacitor. Bypass to ground with 0.1µF ceramic chip capacitor.
REFL (Pins 5, 6):
ADC Low Reference. Short together and
OF (Pin 28):
Over/Under Flow Output. High when an over bypass to pins 3, 4 with a 0.1µF ceramic chip capacitor as or under flow has occurred. close to the pin as possible. Also bypass to pins 3, 4 with
MODE (Pin 29):
Output Format and Clock Duty Cycle an additional 2.2µF ceramic chip capacitor and to ground Stabilizer Selection Pin. Connecting MODE to GND selects with a 1µF ceramic chip capacitor. offset binary output format and turns the clock duty cycle
VDD (Pins 7, 32):
3V Supply. Bypass to GND with 0.1µF stabilizer off. 1/3 VDD selects offset binary output format ceramic chip capacitors. and turns the clock duty cycle stabilizer on. 2/3 VDD selects 2’s complement output format and turns the clock duty
GND (Pin 8):
ADC Power Ground. cycle stabilizer on. VDD selects 2’s complement output
CLK (Pin 9):
Clock Input. The input sample starts on the format and turns the clock duty cycle stabilizer off. positive edge.
SENSE (Pin 30):
Reference Programming Pin. Connecting
SHDN (Pin 10):
Shutdown Mode Selection Pin. Connect- SENSE to VCM selects the internal reference and a ±0.5V ing SHDN to GND and OE to GND results in normal input range. VDD selects the internal reference and a ±1V operation with the outputs enabled. Connecting SHDN to input range. An external reference greater than 0.5V and GND and OE to VDD results in normal operation with the less than 1V applied to SENSE selects an input range of outputs at high impedance. Connecting SHDN to VDD and ±V OE to GND results in nap mode with the outputs at high SENSE. ±1V is the largest valid input range. impedance. Connecting SHDN to V
V
DD and OE to VDD
CM (Pin 31):
1.5V Output and Input Common Mode Bias. results in sleep mode with the outputs at high impedance. Bypass to ground with 2.2µF ceramic chip capacitor.
OE (Pin 11):
Output Enable Pin. Refer to SHDN pin
GND (Exposed Pad) (Pin 33):
ADC Power Ground. The function. exposed pad on the bottom of the package needs to be soldered to ground. 2229fa 8
U U U PI FU CTIO S AIN+ (Pin 1):
Positive Differential Analog Input.
NC (Pins 12, 13):
Do Not Connect These Pins.
AIN- (Pin 2):
Negative Differential Analog Input.
D0–D11 (Pins 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26, REFH (Pins 3, 4):
ADC High Reference. Short together and
27):
Digital Outputs. D11 is the MSB. bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as
OGND (Pin 20):
Output Driver Ground. close to the pin as possible. Also bypass to pins 5, 6 with an additional 2.2µF ceramic chip capacitor and to ground
OVDD (Pin 21):
Positive Supply for the Output Drivers. with a 1µF ceramic chip capacitor. Bypass to ground with 0.1µF ceramic chip capacitor.
REFL (Pins 5, 6):
ADC Low Reference. Short together and
OF (Pin 28):
Over/Under Flow Output. High when an over bypass to pins 3, 4 with a 0.1µF ceramic chip capacitor as or under flow has occurred. close to the pin as possible. Also bypass to pins 3, 4 with
MODE (Pin 29):
Output Format and Clock Duty Cycle an additional 2.2µF ceramic chip capacitor and to ground Stabilizer Selection Pin. Connecting MODE to GND selects with a 1µF ceramic chip capacitor. offset binary output format and turns the clock duty cycle
VDD (Pins 7, 32):
3V Supply. Bypass to GND with 0.1µF stabilizer off. 1/3 VDD selects offset binary output format ceramic chip capacitors. and turns the clock duty cycle stabilizer on. 2/3 VDD selects 2’s complement output format and turns the clock duty
GND (Pin 8):
ADC Power Ground. cycle stabilizer on. VDD selects 2’s complement output
CLK (Pin 9):
Clock Input. The input sample starts on the format and turns the clock duty cycle stabilizer off. positive edge.
SENSE (Pin 30):
Reference Programming Pin. Connecting
SHDN (Pin 10):
Shutdown Mode Selection Pin. Connect- SENSE to VCM selects the internal reference and a ±0.5V ing SHDN to GND and OE to GND results in normal input range. VDD selects the internal reference and a ±1V operation with the outputs enabled. Connecting SHDN to input range. An external reference greater than 0.5V and GND and OE to VDD results in normal operation with the less than 1V applied to SENSE selects an input range of outputs at high impedance. Connecting SHDN to VDD and ±V OE to GND results in nap mode with the outputs at high SENSE. ±1V is the largest valid input range. impedance. Connecting SHDN to V
V
DD and OE to VDD
CM (Pin 31):
1.5V Output and Input Common Mode Bias. results in sleep mode with the outputs at high impedance. Bypass to ground with 2.2µF ceramic chip capacitor.
OE (Pin 11):
Output Enable Pin. Refer to SHDN pin
GND (Exposed Pad) (Pin 33):
ADC Power Ground. The function. exposed pad on the bottom of the package needs to be soldered to ground. 2229fa 8
