Datasheet LTC2240-12 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 12-Bit, 170Msps ADC |
| Pages / Page | 30 / 10 — PIN FUNCTIONS. (LVDS Mode). OVDD (Pins 26, 34, 42, 49):. AIN+ (Pins 1, … |
| File Format / Size | PDF / 555 Kb |
| Document Language | English |
PIN FUNCTIONS. (LVDS Mode). OVDD (Pins 26, 34, 42, 49):. AIN+ (Pins 1, 2):. AIN– (Pins 3, 4):. CLKOUT–/CLKOUT+ (Pins 35 to 36):
Model Line for this Datasheet
Text Version of Document
LTC2240-12
PIN FUNCTIONS (LVDS Mode) OVDD (Pins 26, 34, 42, 49):
Positive Supply for the Out-
AIN+ (Pins 1, 2):
Positive Differential Analog Input. put Drivers. Bypass to ground with 0.1μF ceramic chip capacitor.
AIN– (Pins 3, 4):
Negative Differential Analog Input.
CLKOUT–/CLKOUT+ (Pins 35 to 36):
LVDS Data Valid
REFHA (Pins 5, 6):
ADC High Reference. Bypass to Output. Latch data on rising edge of CLKOUT–, falling Pins 7, 8 with 0.1μF ceramic chip capacitor, to Pins 11, edge of CLKOUT+. 12 with a 2.2μF ceramic capacitor and to ground with 1μF ceramic capacitor.
OF–/OF+ (Pins 55 to 56):
LVDS Over/Under Flow Output. High when an over or under fl ow has occurred.
REFLB (Pins 7, 8):
ADC Low Reference. Bypass to Pins 5, 6 with 0.1μF ceramic chip capacitor. Do not connect to
LVDS (Pin 57):
Output Mode Selection Pin. Connecting Pins 11, 12. LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3V
REFHB (Pins 9, 10):
ADC High Reference. Bypass to DD selects demux CMOS mode with simultaneous update. Connecting LVDS to 2/3V Pins 11, 12 with 0.1μF ceramic chip capacitor. Do not DD selects demux CMOS mode with interleaved update. Connecting LVDS to V connect to Pins 5, 6. DD selects LVDS mode.
REFLA (Pins 11, 12):
ADC Low Reference. Bypass to
MODE (Pin 58):
Output Format and Clock Duty Cycle Pins 9, 10 with 0.1μF ceramic chip capacitor, to Pins 5, Stabilizer Selection Pin. Connecting MODE to 0V selects 6 with a 2.2μF ceramic capacitor and to ground with 1μF offset binary output format and turns the clock duty cycle ceramic capacitor. stabilizer off. Connecting MODE to 1/3VDD selects offset
VDD (Pins 13, 14, 15, 62, 63):
2.5V Supply. Bypass to binary output format and turns the clock duty cycle stabilizer GND with 0.1μF ceramic chip capacitors. on. Connecting MODE to 2/3VDD selects 2’s complement
GND (Pins 16, 61, 64):
ADC Power Ground. output format and turns the clock duty cycle stabilizer on. Connecting MODE to V
ENC+ (Pin 17):
Encode Input. Conversion starts on the DD selects 2’s complement output format and turns the clock duty cycle stabilizer off. positive edge.
SENSE (Pin 59):
Reference Programming Pin. Connecting
ENC– (Pin 18):
Encode Complement Input. Conversion SENSE to V starts on the negative edge. Bypass to ground with 0.1μF CM selects the internal reference and a ±0.5V input range. Connecting SENSE to V ceramic for single-ended encode signal. DD selects the internal reference and a ±1V input range. An external reference
SHDN (Pin 19):
Shutdown Mode Selection Pin. Connecting greater than 0.5V and less than 1V applied to SENSE SHDN to GND and OE to GND results in normal operation selects an input range of ±VSENSE. ±1V is the largest valid with the outputs enabled. Connecting SHDN to GND and input range. OE to VDD results in normal operation with the outputs at
V
high impedance. Connecting SHDN to V
CM (Pin 60):
1.25V Output and Input Common Mode DD and OE to GND Bias. Bypass to ground with 2.2μF ceramic chip capacitor. results in nap mode with the outputs at high impedance. Connecting SHDN to V
GND (Exposed Pad) (Pin 65):
ADC Power Ground. The DD and OE to VDD results in sleep mode with the outputs at high impedance. exposed pad on the bottom of the package needs to be
OE
soldered to ground.
(Pin 20):
Output Enable Pin. Refer to SHDN pin function.
D0–/D0+ to D11–/D11+ (Pins 21, 22, 23, 24, 27, 28, 29, 30, 31, 32, 37, 38, 39, 40, 43, 44, 45, 46, 47, 48, 51, 52, 53, 54):
LVDS Digital Outputs. All LVDS outputs re- quire differential 100Ω termination resistors at the LVDS receiver. D11–/D11+ is the MSB.
OGND (Pins 25, 33, 41, 50):
Output Driver Ground. 224012fd 10 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION CONVERTER CHARACTERISTICS ANALOG INPUT DYNAMIC ACCURACY INTERNAL REFERENCE CHARACTERISTICS DIGITAL INPUTS AND DIGITAL OUTPUTS POWER REQUIREMENTS TIMING CHARACTERISTICS ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS FUNCTIONAL BLOCK DIAGRAM TIMING DIAGRAMS APPLICATIONS INFORMATION PACKAGE DESCRIPTION REVISION HISTORY RELATED PARTS
PIN FUNCTIONS (LVDS Mode) OVDD (Pins 26, 34, 42, 49):
Positive Supply for the Out-
AIN+ (Pins 1, 2):
Positive Differential Analog Input. put Drivers. Bypass to ground with 0.1μF ceramic chip capacitor.
AIN– (Pins 3, 4):
Negative Differential Analog Input.
CLKOUT–/CLKOUT+ (Pins 35 to 36):
LVDS Data Valid
REFHA (Pins 5, 6):
ADC High Reference. Bypass to Output. Latch data on rising edge of CLKOUT–, falling Pins 7, 8 with 0.1μF ceramic chip capacitor, to Pins 11, edge of CLKOUT+. 12 with a 2.2μF ceramic capacitor and to ground with 1μF ceramic capacitor.
OF–/OF+ (Pins 55 to 56):
LVDS Over/Under Flow Output. High when an over or under fl ow has occurred.
REFLB (Pins 7, 8):
ADC Low Reference. Bypass to Pins 5, 6 with 0.1μF ceramic chip capacitor. Do not connect to
LVDS (Pin 57):
Output Mode Selection Pin. Connecting Pins 11, 12. LVDS to 0V selects full rate CMOS mode. Connecting LVDS to 1/3V
REFHB (Pins 9, 10):
ADC High Reference. Bypass to DD selects demux CMOS mode with simultaneous update. Connecting LVDS to 2/3V Pins 11, 12 with 0.1μF ceramic chip capacitor. Do not DD selects demux CMOS mode with interleaved update. Connecting LVDS to V connect to Pins 5, 6. DD selects LVDS mode.
REFLA (Pins 11, 12):
ADC Low Reference. Bypass to
MODE (Pin 58):
Output Format and Clock Duty Cycle Pins 9, 10 with 0.1μF ceramic chip capacitor, to Pins 5, Stabilizer Selection Pin. Connecting MODE to 0V selects 6 with a 2.2μF ceramic capacitor and to ground with 1μF offset binary output format and turns the clock duty cycle ceramic capacitor. stabilizer off. Connecting MODE to 1/3VDD selects offset
VDD (Pins 13, 14, 15, 62, 63):
2.5V Supply. Bypass to binary output format and turns the clock duty cycle stabilizer GND with 0.1μF ceramic chip capacitors. on. Connecting MODE to 2/3VDD selects 2’s complement
GND (Pins 16, 61, 64):
ADC Power Ground. output format and turns the clock duty cycle stabilizer on. Connecting MODE to V
ENC+ (Pin 17):
Encode Input. Conversion starts on the DD selects 2’s complement output format and turns the clock duty cycle stabilizer off. positive edge.
SENSE (Pin 59):
Reference Programming Pin. Connecting
ENC– (Pin 18):
Encode Complement Input. Conversion SENSE to V starts on the negative edge. Bypass to ground with 0.1μF CM selects the internal reference and a ±0.5V input range. Connecting SENSE to V ceramic for single-ended encode signal. DD selects the internal reference and a ±1V input range. An external reference
SHDN (Pin 19):
Shutdown Mode Selection Pin. Connecting greater than 0.5V and less than 1V applied to SENSE SHDN to GND and OE to GND results in normal operation selects an input range of ±VSENSE. ±1V is the largest valid with the outputs enabled. Connecting SHDN to GND and input range. OE to VDD results in normal operation with the outputs at
V
high impedance. Connecting SHDN to V
CM (Pin 60):
1.25V Output and Input Common Mode DD and OE to GND Bias. Bypass to ground with 2.2μF ceramic chip capacitor. results in nap mode with the outputs at high impedance. Connecting SHDN to V
GND (Exposed Pad) (Pin 65):
ADC Power Ground. The DD and OE to VDD results in sleep mode with the outputs at high impedance. exposed pad on the bottom of the package needs to be
OE
soldered to ground.
(Pin 20):
Output Enable Pin. Refer to SHDN pin function.
D0–/D0+ to D11–/D11+ (Pins 21, 22, 23, 24, 27, 28, 29, 30, 31, 32, 37, 38, 39, 40, 43, 44, 45, 46, 47, 48, 51, 52, 53, 54):
LVDS Digital Outputs. All LVDS outputs re- quire differential 100Ω termination resistors at the LVDS receiver. D11–/D11+ is the MSB.
OGND (Pins 25, 33, 41, 50):
Output Driver Ground. 224012fd 10 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION CONVERTER CHARACTERISTICS ANALOG INPUT DYNAMIC ACCURACY INTERNAL REFERENCE CHARACTERISTICS DIGITAL INPUTS AND DIGITAL OUTPUTS POWER REQUIREMENTS TIMING CHARACTERISTICS ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS FUNCTIONAL BLOCK DIAGRAM TIMING DIAGRAMS APPLICATIONS INFORMATION PACKAGE DESCRIPTION REVISION HISTORY RELATED PARTS
